- 您現在的位置：買賣IC網 > PDF目錄372950 > XRT73LC00 (Exar Corporation) E3/DS3/STS-1 LINE INTERFACE UNIT PDF資料下載
參數資料
| 型號： | XRT73LC00 |
| 廠商： | Exar Corporation |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | E3/DS3/STS-1線路接口單元 |
| 文件頁數： | 7/53頁 |
| 文件大?。?/td> | 604K |
| 代理商： | XRT73LC00 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
á
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
4
10
RxAVDD
****
Receive Analog Power Supply
11
REGRESET/
(RCLK2INV)
I
Register Reset Input pin (Invert RCLK2 Output - Select):
The function of this pin depends upon whether the XRT73L00 is operating in the
HOST Mode or in the Hardware Mode.
HOST Mode - Register Reset Input pin:
Setting this input pin “Low” causes the XRT73L00 to reset the contents of the
Command Registers to their default settings and operating configuration. This
pin is internally pulled “High”.
Hardware Mode - Invert RCLK2 Output Select:
Setting this input pin “Low” configures the Receive Section of the XRT73L00 to
output the recovered data via the RPOS and RNEG output pins on the rising
edge of the RCLK2 output signal.
Setting this input pin “High” configures the Receive Section to output the recov-
ered data on the falling edge of the RCLK2 output signal.
12
REQDIS
I
Receive Equalization Disable Input:
Setting this input pin “High” disables the Internal Receive Equalizer in the
XRT73L00. Setting this pin “Low” enables the Internal Receive Equalizer. The
guidelines for enabling and disabling the Receive Equalizer are described in
Section 3.2.
N
OTES
:
1. This input pin is ignored if the XRT73L00 is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00 is going to be operating in the
HOST Mode.
13
LOSTHR
I
Loss of Signal Threshold Control:
This input pin is used to select the LOS (Loss of Signal) Declaration and Clear-
ance thresholds for the Analog LOS Detector circuit. Two settings are provided
by forcing this signal to either GND or VDD.
N
OTE
:
This pin is only applicable during DS3 or STS-1 operations.
14
LLB
I
Local Loop-Back Select:
This input pin along with RLB dictates which Loop-Back mode the XRT73L00 is
operating in.
A “High” on this pin with RLB being set to “Low” configures the XRT73L00 to
operate in the Analog Local Loop-Back Mode.
A “High” on this pin with RLB also being set to “High” configures the XRT73L00
to operate in the Digital Local Loop-Back Mode.
N
OTES
:
1. This input pin is ignored if the XRT73L00 is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00 is going to be operating in the
HOST Mode.
PIN DESCRIPTION
P
IN
#
S
YMBOL
T
YPE
D
ESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT73LC00IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00A | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00AIV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT75L03DIV | Telecomm/Datacomm |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT73LC00A | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00AES | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIV | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC00AIV-F | 功能描述:外圍驅動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。