參數(shù)資料
型號(hào): XRT73LC00A
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: E3/DS3/STS-1線路接口單元
文件頁(yè)數(shù): 31/53頁(yè)
文件大?。?/td> 376K
代理商: XRT73LC00A
xr
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.0
28
3.0
Figure 1 indicates that the XRT73LC00A Receive
Section consists of the following blocks:
AGC/Equalizer
Peak Detector
Slicer
Clock Recovery PLL
Data Recovery
HDB3/B3ZS Decoder
The purpose of the XRT73LC00A Receive Section is
to take an incoming attenuated/distorted bipolar sig-
THE RECEIVE SECTION
nal from the line and encode it back into the TTL/
CMOS format where it can be received and pro-
cessed by digital circuitry in the Terminal Equipment.
3.1
I
NTERFACING
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73LC00A
TO
THE
L
INE
By design, the Receive Section of the XRT73LC00A
can be transformer-coupled or capacitive-coupled to
the line. The specification documents for E3, DS3
and STS-1 all specify 75Ohm termination loads when
transmitting over coaxial cable. It is recommended to
interface the Receive Section of the XRT73LC00A to
the line as shown in Figure 17 or Figure 18.
3.2
After the XRT73LC00A has received the incoming
line signal via the RTIP and RRING input pins, the
T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
first block that this signal passes through is the AGC
(Automatic Gain Control) circuit followed by the Re-
ceive Equalizer.
F
IGURE
17. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73LC00A
TO
THE
L
INE
(T
RANSFORMER
-C
OUPLING
)
BNC
1:1
R1
37.4
R2
37.4
RTIP
RRING
C1
0.01uf
RPOS
RNEG
RCLK1
RLOS
RLOL
RxLOS
RxLOL
RxPOS
RxNEG
RxLineClk
T2
F
IGURE
18. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73LC00A
TO
THE
L
INE
(C
APACITIVE
-C
OUPLING
)
R1
75
RTIP
RRING
C1
0.01uF
C2
0.01uF
Receive Line Signal
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