參數(shù)資料
型號(hào)： XRT73LC04AIV-F
廠商： Exar Corporation
文件頁數(shù)： 28/64頁
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 4CH 144LQFP
標(biāo)準(zhǔn)包裝： 60
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
XRT73LC04A
30
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
rence of three (3) consecutive zeros (e.g., "000"). If
the B3ZS Encoder finds an occurrence of three con-
secutive zeros, then it substitutes these three "0’s",
with either a "00V" or a "B0V" pattern.
Where:
"B" represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code; and
"V" represents a Bipolar Violation (e.g., a bipolar
pulse that violates the Alternating Polarity require-
ments of the AMI line code).
The B3ZS Encoder decides whether to substitute
with either the “00V" or the "B0V" pattern in order to
insure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 17 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros
2.3.2
HDB3 Encoding
If the XRT73LC04A is configured to operate in the E3
Mode, then the HDB3/B3ZS Encoder blocks operate
in the HDB3 Mode. When the Encoder is operating in
this mode, it parses through and searches the Trans-
mit Data Stream from the Transmit Logic Block for the
occurrence of four (4) consecutive zeros (e.g.,
"0000"). If the HDB3 Encoder finds an occurrence of
four consecutive zeros, then it substitutes these four
"0’s", with either a "000V" or a "B00V" pattern. The
HDB3 Encoder decides whether to substitute with ei-
ther the "000V" or the "B00V" pattern in order to in-
sure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 18 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) consecutive ze-
ros.
2.3.3
Disabling the HDB3/B3ZS Encoder
The XRT73LC04A HDB3/B3ZS Encoder can be dis-
abled by two methods.
a. Operating in the Hardware Mode.
The HBD3/B3ZS Encoder blocks within all channels
are disabled by setting the CS/(SR/DR) input pin to
"1".
NOTE: By executing this step the HDB3/B3ZS Encoder and
Decoder blocks in all channels of the XRT73LC04A are glo-
bally disabled.
FIGURE 17. AN EXAMPLE OF B3ZS ENCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Line signal
B
V
0
V
0
FIGURE 18. AN EXAMPLE OF HDB3 ENCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Line signal
B
V
0
V
0
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