參數(shù)資料
型號(hào)： XRT75L06D
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： 六通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁(yè)數(shù)： 5/103頁(yè)
文件大?。?/td> 679K
代理商： XRT75L06D
xr
REV. 1.0.4
XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
II
3.4 TRANSMIT PULSE SHAPER............................................................................................................................ 27
F
IGURE
20. T
RANSMIT
P
ULSE
S
HAPE
T
EST
C
IRCUIT
....................................................................................................................... 27
3.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT.................................................................................... 27
3.5 E3 LINE SIDE PARAMETERS .......................................................................................................................... 28
F
IGURE
21. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703....................................................................... 28
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
....................................................... 29
F
IGURE
22. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
.......................... 30
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 30
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .............................. 31
F
IGURE
23. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499................................................................... 31
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 32
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 32
3.6 TRANSMIT DRIVE MONITOR........................................................................................................................... 33
F
IGURE
24. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
............................................................................................................................ 33
3.7 TRANSMITTER SECTION ON/OFF.................................................................................................................. 33
4.0 JITTER................................................................................................................................................... 34
4.1 JITTER TOLERANCE........................................................................................................................................ 34
F
IGURE
25. J
ITTER
T
OLERANCE
M
EASUREMENTS
........................................................................................................................... 34
4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS.................................................................................................. 34
F
IGURE
26. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1................................................................................................................ 35
4.1.2 E3 JITTER TOLERANCE REQUIREMENTS................................................................................................................ 35
F
IGURE
27. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3.............................................................................................................................. 35
T
ABLE
8: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) .................................................................... 36
4.2 JITTER TRANSFER........................................................................................................................................... 36
T
ABLE
9: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
.............................................................................................................. 36
4.3 JITTER ATTENUATOR ..................................................................................................................................... 36
T
ABLE
10: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 37
F
IGURE
28. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 37
4.3.1 JITTER GENERATION.................................................................................................................................................. 37
5.0 DIAGNOSTIC FEATURES..................................................................................................................... 38
5.1 PRBS GENERATOR AND DETECTOR............................................................................................................ 38
F
IGURE
29. PRBS MODE............................................................................................................................................................. 38
5.2 LOOPBACKS .................................................................................................................................................... 39
5.2.1 ANALOG LOOPBACK.................................................................................................................................................. 39
F
IGURE
30. A
NALOG
L
OOPBACK
..................................................................................................................................................... 39
5.2.2 DIGITAL LOOPBACK................................................................................................................................................... 40
F
IGURE
31. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 40
5.2.3 REMOTE LOOPBACK.................................................................................................................................................. 40
F
IGURE
32. R
EMOTE
L
OOPBACK
.................................................................................................................................................... 40
5.3 TRANSMIT ALL ONES (TAOS) ........................................................................................................................ 41
F
IGURE
33. T
RANSMIT
A
LL
O
NES
(TAOS)...................................................................................................................................... 41
6.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 42
T
ABLE
11: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
................................................................................................... 42
F
IGURE
34. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
.................................................................. 42
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS............................................................................ 43
T
ABLE
12: XRT75L06D M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
................................................................................................... 43
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION............................................................................. 44
F
IGURE
35. A
SYNCHRONOUS
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
........................... 45
T
ABLE
13: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
...................................................................................................................... 45
F
IGURE
36. S
YNCHRONOUS
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................. 46
T
ABLE
14: S
YNCHRONOUS
T
IMING
S
PECIFICATIONS
........................................................................................................................ 46
F
IGURE
37. I
NTERRUPT
PROCESS
................................................................................................................................................... 47
6.2.1 HARDWARE RESET: ................................................................................................................................................... 48
T
ABLE
15: R
EGISTER
M
AP
AND
B
IT
N
AMES
.................................................................................................................................... 48
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
......................................................................................................................... 49
T
ABLE
17: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
N
R
EGISTERS
(
N
= 0,1,2,3,4,5) ................................................................... 49
T
ABLE
18: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
N
................................................................................................................... 51
7.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU................................................................. 56
7.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .............................. 56
F
IGURE
38. A S
IMPLE
I
LLUSTRATION
OF
A
DS3
SIGNAL
BEING
MAPPED
INTO
AND
TRANSPORTED
OVER
THE
SONET N
ETWORK
........ 57
7.2 MAPPING/DE-MAPPING JITTER/WANDER.................................................................................................... 58
7.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................... 58
F
IGURE
39. A S
IMPLE
I
LLUSTRATION
OF
THE
SONET STS-1 F
RAME
.............................................................................................. 59
F
IGURE
40. A S
IMPLE
I
LLUSTRATION
OF
THE
STS-1 F
RAME
S
TRUCTURE
WITH
THE
TOH
AND
THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
相關(guān)PDF資料
PDF描述
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03DIV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L06DES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6CH T3/E3/STS1 LIU+DESYNCH 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L06DIB 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU w/DeSynch RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT75L06DIB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L06ES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6 CHT3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L06IB 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
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