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參數(shù)資料
| 型號(hào)： | XRT75L06D |
| 廠商： | Exar Corporation |
| 英文描述： | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 中文描述： | 六通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER |
| 文件頁(yè)數(shù)： | 81/103頁(yè) |
| 文件大小： | 679K |
| 代理商： | XRT75L06D |
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XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
xr
REV. 1.0.4
77
viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper
IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals
(towards the DS3 facility), then it will typically do so in the following manner.
In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".
In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.
However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the Clock-
Signal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper
IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output
via the "Data-Signal".
Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output Clock-
Signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the
Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period.
Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal.
One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within
the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must
handle this type of jitter is presented in “Section 7.8.2, Recommendations on Pre-Processing the Gapped
Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs
of the LIU” on page 88.
7.5
A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3
applications
The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates
that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their
corresponding requirements is summarized in Table 19, below.
T
ABLE
19: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT
PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
S
CENARIO
D
ESCRIPTION
S
CENARIO
N
UMBER
T
ELCORDIA
GR-253-CORE
C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENTS
C
OMMENTS
DS3 De-Mapping
Jitter
0.4UI-pp
Includes effects of De-Mapping and Clock Gapping Jit-
ter
Single Pointer
Adjustment
A1
0.3UI-pp + Ao
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.NOTE: Ao is the amount
of intrinsic jitter that was measured during the "DS3 De-
Mapping Jitter" phase of the Test.
Pointer Bursts
A2
1.3UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Phase Transients
A3
1.2UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
87-3 Pattern
A4
1.0UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
87-3 Add
A5
1.3UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
87-3 Cancel
A5
1.3UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Continuous Pattern
A4
1.0UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT75L06DIB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75L06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75L06IB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R03D | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER |
| XRT75R03DIV | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75L06DES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6CH T3/E3/STS1 LIU+DESYNCH 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75L06DIB | 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU w/DeSynch RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| XRT75L06DIB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75L06ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6 CHT3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75L06IB | 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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