xr
REV. 1.0.4
XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
IV
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06.................................................... 87
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E................................................. 87
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16.................................................. 87
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- (C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................. 87
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F..................................... 87
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17..................................... 87
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07................................... 88
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F............................... 88
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17............................... 88
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07................................... 88
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F.............................. 88
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17.............................. 88
7.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 88
F
IGURE
66. I
LLUSTRATION
OF
MINOR PATTERN P1 .................................................................................................................... 89
F
IGURE
67. I
LLUSTRATION
OF
MINOR PATTERN P2 .................................................................................................................... 90
F
IGURE
68. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
MAJOR PATTERN A.................................................. 90
F
IGURE
69. I
LLUSTRATION
OF
MINOR PATTERN P3 .................................................................................................................... 91
F
IGURE
70. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
PATTERN B............................................................... 91
F
IGURE
71. I
LLUSTRATION
OF
THE
SUPER PATTERN
WHICH
IS
OUTPUT
VIA
THE
"OC-N
TO
DS3" M
APPER
IC............................... 92
F
IGURE
72. S
IMPLE
I
LLUSTRATION
OF
THE
LIU
BEING
USED
IN
A
SONET D
E
-S
YNCHRONIZER
" A
PPLICATION
.................................... 92
7.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS
OF 50MS (PER TELCORDIA GR-253-CORE) ............................................................................................................ 92
T
ABLE
21: M
EASURED
APS R
ECOVERY
T
IME
AS
A
FUNCTION
OF
DS3
PPM
OFFSET
......................................................................... 93
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07................................... 93
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F.............................. 93
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17.............................. 93
7.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END
CUSTOMER'S SITE..................................................................................................................................................... 94
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07................................... 94
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F..................................... 94
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17..................................... 94
8.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 95
T
ABLE
22: A
BSOLUTE
M
AXIMUM
R
ATINGS
....................................................................................................................................... 95
T
ABLE
23: DC E
LECTRICAL
C
HARACTERISTICS
: .............................................................................................................................. 95
APPENDIX A................................................................................................................... 96
T
ABLE
24: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 96
T
ABLE
25: T
RANSFORMER
D
ETAILS
................................................................................................................................................ 96
ORDERING INFORMATION ................................................................................................................. 98
P
ACKAGE
D
IMENSIONS
- 23
X
23
MM
217 L
EAD
BGA
PACKAGE
.................................................................. 98