參數(shù)資料
型號(hào): XRT75L06DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA217
封裝: 23 X 23 MM, BGA-217
文件頁(yè)數(shù): 93/103頁(yè)
文件大?。?/td> 679K
代理商: XRT75L06DIB
XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
xr
REV. 1.0.4
89
Our simulation results indicate that Jitter Attenuator PLL (within the LIU LIU IC) will have no problem handling
and processing the "Data-Signal" and "Clock-Signal" from a Mapper IC/ASIC if no pre-processing has been
performed on these signals. In order words, our simulation results indicate that the Jitter Attenuator PLL
(within the LIU IC) will have no problem handling the "worst-case" of 59 consecutive bits of no clock pulses in
the "Clock-Signal (due to the Mapper IC processing the TOH bytes, an Incrementing Pointer-Adjustment-
induced "stuffed-byte", the POH byte, and the two fixed-stuff bytes within the STS-1 SPE, etc), immediately
followed be processing clusters of DS3 data-bits (as shown in Figure 45) and still comply with the "Category I
Intrinsic Jitter Requirements per Telcordia GR-253-CORE for DS3 applications.
N
OTE
:
If this sort of "pre-processing" is already supported by the Mapper device that you are using, then no further action
is required by the user.
7.8.2.2
OUR PRE-PROCESSING RECOMMENDATIONS
For the time-being, we recommend that the customer implement the "pre-processing" of the DS3 "Data-Signal"
and "Clock-Signal" as described below. Currently we are aware that some of the Mapper products on the
Market do implement this exact "pre-processing" algorithm. However, if the customer is implementing their
Mapper Design in an ASIC or FPGA solution, then we strongly recommend that the user implement the
necessary logic design to realize the following recommendations.
Some time ago, we spent some time, studying (and then later testing our solution with) the PM5342 OC-3 to
DS3 Mapper IC from PMC-Sierra. In particular, we wanted to understand the type of "DS3 Clock" and "Data"
signal that this DS3 to OC-3 Mapper IC outputs.
During this effort, we learned the following.
1.
This "DS3 Clock" and "Data" signal, which is output from the Mapper IC consists of two major "repeating"
patterns (which we will refer to as "MAJOR PATTERN A" and "MAJOR PATTERN B". The behavior of
each of these patterns is presented below.
MAJOR PATTERN A
MAJOR PATTERN A consists of two "sub" or minor-patterns, (which we will refer to as "MINOR PATTERN P1
and P2).
MINOR PATTERN P1 consists of a string of seven (7) clock pulses, followed by a single gap (no clock pulse).
An illustration of MINOR PATTERN P1 is presented below in Figure 66.
It should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an
"instantaneously frequency of 51.84MHz).
MINOR Pattern P2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock
pulse). An illustration of Pattern P2 is presented below in Figure 67.
F
IGURE
66. I
LLUSTRATION
OF
MINOR PATTERN P1
1 2 3 4 5
6 7
Missing Clock Pulse
相關(guān)PDF資料
PDF描述
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03DIV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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