參數(shù)資料
型號(hào): XRT75R06IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PBGA217
封裝: 23 X 23 MM, BGA-217
文件頁(yè)數(shù): 58/63頁(yè)
文件大?。?/td> 350K
代理商: XRT75R06IB
XRT75R06
REV. 1.0.0
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
55
0x06 (ch 0)
0x16 (ch 1)
0x26 (ch 2)
0x36 (ch 3)
0x46 (ch 4)
0x56 (ch 5)
R/W
Block Con-
trol
D0
SR/DR_n
Setting this bit configures the Receiver and Trans-
mitter in Single-Rail (NRZ) mode.
N
OTE
:
See section 4.0 for detailed description.
0
D1
STS-1/
DS3_n
Setting this bit configures the channel into STS-1
mode.
N
OTE
:
This bit field is ignored if the channel is con-
figured to operate in E3 mode.
0
D2
E3_n
Setting this bit configures the channel in E3 mode.
0
D3
LLB_n
Setting this bit configures the channel in Local Loop-
back mode.
0
D4
RLB_n
This bit along with LLB_n determine the diagnostic
mode as shown in the table below.
0
D5
PRBSEN_
n
Setting this bit enables the PRBS generator/detec-
tor. When in E3 mode, an unframed 2
23
-1 pattern is
used. For DS3 and STS-1, unframed 2
15
-1 pattern is
used. This mode of operation will use TCLK for tim-
ing. One should insure that a stable frequency is
provided. Looping this signal back to its own receive
channel and using RCLK to generate TCLK will
cause an unstable condition and should be avoided.
0
D6
CLKOUTE
N_n
Set this bit to enable the CLKOUTs on a per channel
basis. The frequency of the output clock is depen-
dent on the configuration of the channels, either E3,
DS3 or STS-1.
0
D7
Reserved
T
ABLE
18: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
N
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
RLB_n
0
0
Loopback Mode
Normal Operation
Analog Local
LLB_n
0
1
1
1
Remote
Digital
0
1
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