參數(shù)資料
型號(hào): XRT75R12
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與抖動(dòng)衰減器
文件頁(yè)數(shù): 29/89頁(yè)
文件大?。?/td> 457K
代理商: XRT75R12
PRELIMINARY
XRT75R12
REV. P1.0.2
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
26
3.5.5
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n
pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “1”.
Muting the Recovered Data with LOS condition:
N
OTE
:
When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
3.6
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or
contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on
the RLCV_n output pins to indicate line code violation.
B3ZS/HDB3 Decoder
F
IGURE
12. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle
45
50
55
%
RxClk Frequency
E3
DS-3
STS-1
34.368
44.736
51.84
MHz
MHz
MHz
t
RRX
RxClk rise time (10% o 90%)
2
4
ns
t
FRX
RxClk falling time (10% to 90%)
2
4
ns
t
CO
RxClk to RPOS/RNEG delay time
4
ns
t
LCVO
RxClk to rising edge of LCV output delay
2.5
ns
RxClk
t
RRX
t
FRX
RPOS or
RNEG
LCV
t
LCVO
t
CO
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