參數(shù)資料
型號: XRT75R12
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與抖動衰減器
文件頁數(shù): 65/89頁
文件大小: 457K
代理商: XRT75R12
PRELIMINARY
XRT75R12
REV. P1.0.2
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
62
T
ABLE
21: C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR224 (A
DDRESS
L
OCATION
= 0
X
E0)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved
Reserved
Channel 11
Interrupt
Enable
Channel 10
Interrupt
Enable
Channel 9
Interrupt
Enable
Channel 8
Interrupt
Enable
Channel 7
Interrupt
Enable
Channel 6
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7,6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Enable
Channel 10 Interrupt Enable
Channel 9 Interrupt Enable
Channel 8 Interrupt Enable
Channel 7 Interrupt Enable
Channel 6 Interrupt Enable
R/W
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
To enable Channel n for Interrupt Generation at the Channel
Level
To disable all Interrupts associated with Channel n within the
XRT75R12
This is a "master" enable bit for
each
channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to
the Host via the INT pin.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user
must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved Reserved
Channel 5
Interrupt Status
Channel 4
Interrupt Status
Channel 3
Interrupt Status
Channel 2
Interrupt Status
Channel 1
Interrupt Status
Channel 0
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
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