參數(shù)資料
型號(hào)： XRT75VL00IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 36/50頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 1CH 52TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-TQFP（10x10）
包裝： 帶卷 (TR)
XRT75VL00
39
REV. 1.0.6
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
0x01
R/W
D0
DMOIE
Writing a “1” to this bit field enables the DMO inter-
rupt and triggers an interrupt when the transmitter
driver fails. Writing a “0” disables the interrupt.
0
D1
RLOSIE
Writing a “1” to this bit field enables the RLOS inter-
rupt and triggers an interrupt when the RLOS condi-
tion occurs. Writing a “0” disables the interrupt.
0
D2
RLOLIE
Writing a “1” to this bit field enables the RLOL inter-
rupt and triggers an interrupt when RLOL condition
occurs. Writing a “0” disables the interrupt.
0
D3
FLIE
Writing a “1” to this bit field enables the FL interrupt
and triggers an interrupt when the FIFO Limit of the
Jitter Attenuator is within 2 bits of overflow/underflow
condition. Writing a “0” disables the interrupt.
NOTE:
This bit field is ignored when the Jitter
Attenuator is disabled.
0
D4
PRBSIE
Writing a “1” to this bit enables the PRBS bit error
interrupt.
0
D5
CNT_SATIE
Writing a “1” to this bit enables the PRBS error-
counter saturation interrupt. When the PRBS error
counter reaches 0xFFFF, an interrupt will be gener-
ated.
0
0x02
Reset
Upon
Read
D0
DMOIS
This bit is set to “1” every time a DMO status change
has occurred since the last cleared interrupt.This bit
is cleared when read.
0
D1
RLOSIS
This bit is set to “1” every time a RLOS status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D2
RLOLIS
This bit is set to “1” every time a RLOL status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D3
FLIS
This bit is set to “1” every time a FIFO Limit status
change has occurred since the last cleared interrupt.
This bit is cleared when read.
0
D4
PRBSIS
This bit is set to “1” when a PRBS bit error
is
detected. This bit is cleared when read.
0
D5
CNT_SATIS
This bit is set to “1” when the PRBS error counter has
saturated (0xFFFF). This bit is cleared when read.
0
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
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