XRT75VL00
13
REV. 1.0.6
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
6
JA0
I
Disable Jitter Attenuator/FIFO Size Select::
In Hardware Mode, this pin along with JA1 pin provides the following functions
in the table below.
NOTE: This pin is internally pulled down.
7
JA1
I
Disable Jitter Attenuator/FIFO Size Select:
In Hardware Mode, this pin along with JA0 pin provides the functions in the table
above.
NOTE: This pin is internally pulled down.
8
JA Tx/Rx
I
Jitter Attenuator Select:
In Hardware Mode setting this pin “High” selects the Jitter Attenuator in the
Transmit path and setting “Low” selects in Receive path.
NOTE: This pin is internally pulled down.
JA0
0
Operation
16 bit FIFO
32 bit FIFO
JA1
0
1
Disable Jitter
Attenuator
Disable Jitter
Attenuator
0
1