XRT75VL00
42
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.6
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
0x07
R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
ator as shown in the table below.
0
D1
JATx/Rx
Writing a “1” to this bit selects the Jitter Attenuator in
the Transmit Path. A “0” selects in the Receive Path.
0
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
uator as shown in the table.
0
D3
PNTRST
Setting this bit to “1” resets the Read and Write point-
ers of the jitter attenuator FIFO.
0
0x08
Reserved
ADDRESS
(HEX)
TYPE
BIT
LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x20
R/W
D0
INTEN
Bit 0 = INTEN Writing a “1” to this bit enables the
interrupts.
0
0x21
Read
Only
D0
INTST
Bit 0 = INTST bit is set to “1” if an interrupt service is
required. The source level interrupt status register is
read to determine the cause of interrupt.
0
0x22 -
0x2F
Reserved
0x30
Reset
Upon
Read
D[7:0]
PRBSmsb
PRBS error counter MSB [15:8]
0x31
Reset
Upon
Read
D[7:0]
PRBSlsb
PRBS error counter LSB [7:0]
0x32-
0x37
Reserved
0x38
Read
Only
D[7:0]
PRBShold
PRBS Holding Register
0x39-
0x3D
Reserved
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
JA0
0
Mode
16 bit FIFO
32 bit FIFO
JA1
0
1
Disable Jitter
Attenuator
0
1
Disable Jitter
Attenuator