參數(shù)資料
型號: XRT79L72IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述: ATM NETWORK INTERFACE, PBGA456
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁數(shù): 2/72頁
文件大?。?/td> 441K
代理商: XRT79L72IB
XRT79L72
REV. P1.0.2
PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
xr
2
T
RANSMIT
P
ACKET
P
ROCESSING
Inserts PPP packets into data stream
Maps HDLC data stream directly into DS3 or E3 frame
Extracts in-band messaging packets
Supports CRC-16/32, HDLC flag and Idle sequence generation
R
ECEIVE
P
ACKET
P
ROCESSING
Extracts HDLC data stream from DS3 or E3 frame
Inserts in-band messaging packets
Detects and removes HDLC flags
U
TOPIA
/ S
YSTEM
I
NTERFACE
8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz.
Compliant with ATM Forum UTOPIA II interface
Programmable FIFO size for both Transmit and Receive direction
Compliant to POS-PHY Level 2 interface
S
ERIAL
I
NTERFACE
Serial clock and data interface for accessing DS3/E3 framer
Serial clock and data interface for accessing cell/packet processor
APPLICATIONS
Digital Access and Cross Connect Systems
3G Base Stations
DSLAMs
Digital, ATM, WAN and LAN Switches
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT79L72
Clock &
PData
PrRecov ery
Jitter
Attenuator
Rx DS3/
E3
Framer
PLCP &
Overhead
UTOPIA/
POS-PHY
Interface
HDLC
Controller
2
Receiver Block
T
T
T
T
T
JTAG Test Port
AGC/
Equalizer
RTIP
RRING
Transmitter Block
ATM Cell
Processor
or PPP
Processor
UTOPIA/
POS-PHY
Interface
ATM Cell
Processor
or PPP
Processor
HDLC
Controller
PLCP &
Overhead
Tx DS3/
E3
Framer
Jitter
Attenuator
Timing
Control
Pulse
Shaper
TTIP
TRING
Microprocessor Interface
P
I
B
A
A
C
W
R
D
T
D
R
12.288
MHz
ClkIN
Clock
Synthesizer
E3CLK
DS3CLK
Receive
Utopia
POS-PHY
Interface
Transmit
Utopia
POS-PHY
Interface
Channel 1 of 2
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