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參數(shù)資料
| 型號(hào)： | XRT79L72IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | ATM NETWORK INTERFACE, PBGA456 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456 |
| 文件頁(yè)數(shù)： | 39/72頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | XRT79L72IB |
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xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L72
REV. P1.0.2
36
B16
RxUPrty/
RxPPrty
O
Receive UTOPIA Interface - Parity Output pin/Receive POS-PHY Interface -
Parity Output:
The function of this output pin depends upon whether the XRT79L72 has been
configured to operate in the ATM UNI or the PPP Modes.
ATM UNI Mode - RxUPrty:
The Receive UTOPIA interface block will compute the odd-parity value of each
byte (or word) that it will place in the Receive UTOPIA Data Bus. This odd-par-
ity value will be output on this pin, while the corresponding byte (or word) is
present on the Receive UTOPIA Data Bus
PPP Mode - RxPPrty:
The Receive POS-PHY Interface block will compute the odd-parity value of
each byte (or word) that it will place in the Receive POS-PHY Data Bus. This
odd parity value will be output on this pin, which the corresponding byte (or
word) is present on the Receive POS-PHY Data Bus.
N
OTE
:
This output pin will be in-active if the user has configured the XRT79L72
device to operate in either the Clear-Channel Framer or in the High-Speed
HDLC Controller Modes.
E13
RxPEOP
O
Receive POS-PHY Interface - End of Packet:
The XRT79L72 drives this output pin "High" whenever the last byte of a given
Packet is being output via the RxPData[15:0] data bus.
N
OTES
:
1. This output pin is only valid when the XRT79L72 is configured to oper-
ate in the PPP Mode.
2. This output pin is only valid when the Receive POS-PHY Interface -
Read Enable Output pin.
A9
RxPDVAL
O
Receive POS-PHY Interface Signal Valid Indicator:
This output signal indicates whether or not the Receive POS-PHY Interface sig-
nals (e.g., PRData[15:0], RxPSOP, RxPEOP, RxPPrty, RxPERR) are valid.
This output pin will be driven "High", when these signals are valid. Conversely,
this output pin will be driven "Low" when these signals are NOT valid.
N
OTE
:
This output pin is only active if the XRT79L72 has been configured to
operate in the PPP Mode.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT79L73 | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L73IB | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L73 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L73IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
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