XRT79L72
REV. P1.0.2
PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
xr
29
B1
D21
RxCellRxed
_0
RxCellRxed
_1
O
O
Receive Cell Processor - Cell Received Indicator:
These output pins pulse "High" each time the Receive Cell Processor receives
a new cell from the Receive PLCP Processor or the Receive DS3/E3 Framer
block.
These output pins are only active if the XRT79L72 has been configured to oper-
ate in the ATM UNI Mode.
N1
J24
RxPOH
_0/
RxSer
_0
RxPOH
_1
/
RxSer
_1
O
O
Receive PLCP Path Overhead Output pin/Receive Serial Output pin:
The function of these outputs depend upon whether the XRT79L72 has been
configured to operate in the ATM/PLCP Mode or in the Clear-Channel Framer
Mode.
ATM/PLCP Mode - RxPOH:
These output pins along with the RxPOHClk, RxPOHFrame and RxPOHIns
pins comprise the Receive PLCP Frame POH Byte serial output port. For each
PLCP frame, that is received by the Receive PLCP Processor, this serial output
port will output the contents of all 12 POH (Path Overhead) bytes. The data that
is output via these pins are updated on the rising edge of the RxPOHClk output
clock signals. The RxPOHFrame pin will pulse "High" whenever the first bit of
the Z6 byte is being output via these output pins.
Clear-Channel Framer Mode - RxSer:
If the XRT79L72 is configured to operate in the Clear-Channel Framer/Serial
Mode, then the chip will output all received data, via these output pins. These
output signals will be updated upon the rising edge of RxClk.
N
OTE
:
The user should either configure the XRT79L72 to operate in the
Gapped-Clock Mode, or validate the sampling of each bit from the RxSer out-
put with the state of RxOHInd' output pin, in order to prevent the local terminal
equipment from sampling overhead bits.
These output pins are only active if the XRT79L72 has been configured to oper-
ate in the ATM/PLCP or the Clear-Channel Framer/Serial Mode. These pins
are inactive for all remaining modes of operation.
P
IN
#
N
AME
TYPE
D
ESCRIPTION