- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376462 > XRT79L73 (Exar Corporation) 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT79L73 |
| 廠商： | Exar Corporation |
| 英文描述： | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 3 -通道DS3/E3自動(dòng)柜員機(jī)用戶到網(wǎng)絡(luò)接口/ Combo IC對(duì)購買力平價(jià) |
| 文件頁數(shù)： | 26/71頁 |
| 文件大小： | 495K |
| 代理商： | XRT79L73 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
XRT79L73
REV. P1.0.0
PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
t
24
P
IN
#
N
AME
TYPE
D
ESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE PINS
M2
H23
P5
RxAIS1/
RxNib1_2/
RxHDLCDat1_2
RxAIS2/
RxNib2_2/
RxHDLCDat2_2
RxAIS3/
RxNib3_2/
RxHDLCDat3_2
O
O
O
Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/
Receive HDLC Controller Data Bus - Bit 2 output pin:
The function of these output pins depend upon whether the XRT79L73 has
been configured to operate in the Clear-Channel Framer/Nibble-Parallel Inter-
face Mode, the High-Speed HDLC Controller Mode, or in the other modes.
Other Modes - RxAIS:
These output pins are driven "High" whenever the Receive Section of the
XRT79L73 has detected and is currently declaring an AIS (Alarm Indicator Sig-
nal) condition.
Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2:
If the XRT79L73 is configured to operate in the Nibble-Parallel Mode, then
these output pins will function as the bit 2 output from the Receive Nibble-Paral-
lel output interface. The Receive Payload Data Output Interface block will out-
put these signals (along with RxNibn_0, RxNibn_1, and RxNibn_3) upon the
rising edge of the RxClk output signals.
High-Speed HDLC Controller Mode - RxHDLCDat_2:
These output pins along with RxHDLCDatn_[7:3] and RxHDLCDatn_[1:0] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user's
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT79L73IB | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時(shí)鐘同步設(shè)備/調(diào)整器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L73IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。