XRT79L73
REV. P1.0.0
PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
t
A
TABLE OF CONTENTS
HARDWARE MANUAL ......................................................................................................1
GENERAL
F
EATURES
:......................................................................................................................................1
Line Interface Unit .......................................................................................................................................................1
DS3/E3 Framer............................................................................................................................................................1
ATM/PPP PROTOCOL PROCESSOR........................................................................................................................1
Transmit Cell Processing.............................................................................................................................................1
Receive Cell Processing..............................................................................................................................................1
Transmit Packet Processing........................................................................................................................................2
Receive Packet Processing.........................................................................................................................................2
Utopia/ System Interface .............................................................................................................................................2
Serial Interface ............................................................................................................................................................2
APPLICATIONS...........................................................................................................................................2
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT79L73 ............................................................................................................................... 2
P
RODUCT
O
RDERING
I
NFORMATION
................................................................................................................2
T
ABLE OF
C
ONTENTS
..........................................................................................................A
P
IN
D
ESCRIPTIONS
.........................................................................................................................................4
M
ICROPROCESSOR
I
NTERFACE
.......................................................................................................................4
T
EST AND
D
IAGNOSTIC
...................................................................................................................................6
G
ENERAL
P
URPOSE
I
NPUT AND
O
UTPUT
P
INS
.................................................................................................7
T
RANSMIT
S
YSTEM
S
IDE
I
NTERFACE
P
INS
.......................................................................................................7
R
ECEIVE
S
YSTEM
S
IDE
I
NTERFACE
P
INS
.......................................................................................................24
T
RANSMIT
L
INE
S
IDE
S
IGNALS
......................................................................................................................40
R
ECEIVE
L
INE
S
IDE
S
IGNALS
........................................................................................................................42
ELECTRICAL CHARACTERISTICS................................................................................46
AC ELECTRICAL CHARACTERISTIC INFORMATION..................................................46
MICROPROCESSOR INTERFACE TIMING
FOR
R
EVISION
A S
ILICON
......................................................46
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE....................................................46
T
ABLE
1: DC ELECTRICAL CHARACTERISTICSS..................................................................................................................... 46
Applies to all TTL-Level Input and CMOS Level Output pins - Ambient Temperature = 25°C..................................46
F
IGURE
2. A
SYNCHRONUS
M
ODE
1 - I
NTEL TYPE
P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
)............................................................ 46
F
IGURE
3. A
SYNCHRONUS
M
ODE
1 - I
NTEL TYPE
P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
) ............................................................. 47
T
ABLE
2: T
IMING
I
NFORMATION FOR THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN CONFIGURED TO OPERATE IN THE
I
NTEL
A
SYNCHRONOUS
M
ODE
............................................................................................................................................................................ 47
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K)
MODE................................................................................................................................48
F
IGURE
4. A
SYNCHRONUS
M
ODE
2 - M
OTOROLA
68K P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
) .................................................... 48
F
IGURE
5. A
SYNCHRONUS
M
ODE
2 - M
OTOROLA
68 P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
)........................................................ 48
MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE49
T
ABLE
3: T
IMING
I
NFORMATION FOR THE
M
ICROPROCESSOR
I
NTERFACE WHEN CONFIGURED TO OPERATE IN THE
M
OTOROLA
(68K) A
SYN
-
CHRONOUS
M
ODE
........................................................................................................................................................... 49
F
IGURE
6. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE TIMING
(W
RITE
C
YCLE
)......................................................... 49
F
IGURE
7. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE TIMING
(R
EAD
C
YCLE
)........................................................... 50
T
ABLE
4: T
IMING
I
NFORMATION FOR THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN CONFIGURED TO OPERATE IN THE
IBM P
OWER
PC403
M
ODE
............................................................................................................................................................................ 50
DS3/E3 LIU INTERFACE - LINE SIDE ELECTRICAL CHARACTERISTIC INFORMATION
51
E3 L
INE
S
IDE
P
ARAMETERS
.........................................................................................................................51
F
IGURE
8. P
ULSE
M
ASK FOR
E3 (34.368M
BPS
) I
NTERFACE AS PER
ITU-T G.703........................................................................... 51
T
ABLE
5: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
........................................................ 51
DS3 L
INE
S
IDE
P
ARAMETERS
.......................................................................................................................52
F
IGURE
9. B
ELLCORE
GR-499-CORE P
ULSE
T
EMPLATE
R
EQUIREMENTS FOR
DS3 A
PPLICATIONS
.................................................. 52
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 53
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 53
TRANSMIT UTOPIA INTERFACE....................................................................................54
F
IGURE
10. T
IMING
D
IAGRAM FOR THE
T
RANSMIT
UTOPIA I
NTERFACE
B
LOCK
................................................................................ 54
T
ABLE
8: T
IMING
I
NFORMATION FOR THE
T
RANSMIT
UTOPIA I
NTERFACE
B
LOCK
............................................................................. 54