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參數(shù)資料
| 型號： | XRT79L73 |
| 廠商： | Exar Corporation |
| 英文描述： | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 3 -通道DS3/E3自動柜員機用戶到網(wǎng)絡接口/ Combo IC對購買力平價 |
| 文件頁數(shù)： | 36/71頁 |
| 文件大?。?/td> | 495K |
| 代理商： | XRT79L73 |
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XRT79L73
REV. P1.0.0
PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
t
34
D15
RxUClav/RxPPA
O
Receive UTOPIA - Cell Available/Receive POS-PHY Interface - Packet
Available:
The function of this output pin depends upon whether the XRT79L73 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClav - Receive UTOPIA Interface - Cell Available Indi-
cator Output:
The Receive UTOPIA Interface block will assert this output pin in order to indi-
cate that the RxFIFO has some ATM cell data that needs to be read out by the
ATM Layer Processor. This signal will be asserted (e.g., toggles to a logic
"HIGH" level) if the RxFIFO contains at least one full ATM cell of data. This sig-
nal toggle "low" if the RxFIFO is depleted of data, or if it contains less than one
full cell of data. The exact behavior of the RxUClav output pin, as a function of
"UTOPIA Level" is presented below.
Multi-PHY Operation - UTOPIA Level 2:
When the XRT79L73 device is operating in a Multi-PHY Application and is con-
figured to operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated
until the RxUClk cycle following the assertion of a valid address on the Receive
UTOPIA Address bus input pins (e.g., if the contents on the Receive UTOPIA
Address bus pins , RxUAddr[4:0], match that which have been assigned to this
particular Receive UTOPIA Interface block). Afterwards, this output pin will be
driven either "high" or "low" depending upon the current fill status of the
RxFIFO.
Multi-PHY Operation - UTOPIA Level 3:
When the XRT79L73 device is operating in a Multi-PHY Application, then this
signal will be tri-stated until two RxUClk cycles following the assertion of a valid
address on the Receive UTOPIA Address bus input pins (e.g., if the contents of
the Receive UTOPIA Address bus input pins, RxUAddr[4:0], match that which
have been assigned to this particular Receive UTOPIA Interface block). After-
wards, this output pin will be driven either "high" or "low" depending upon the
current fill status of the RxFIFO.PPP Mode - RxPPA - Receive POS-PHY Inter-
face - Packet Available Indicator OutputThe XRT79L73 device will drive this
output pin "high" whenever a (programmable) number of bytes of incoming PPP
Packet data are available to be read from the RxFIFO by the Link Layer Proces-
sor. The exact behavior of the RxPPA output pin, as a function of "POS-PHY
Level" is presented below.
POS-PHY Level 2:
When the XRT79L73 device is configured to operate in the POS-PHY Level 2
Mode, then this signal will be tri-stated until the RxPClk cycle following the
assertion of a valid address on the Receive POS-PHY Address bus input pins
(e.g., if the contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0],
match that which have been assigned to this particular Receive POS-PHY Inter-
face block). Afterwards, this output pin will be driven either "high" or "low"
depending upon the current fill status of the RxFIFO.
POS-PHY Level 3:
When the XRT79L73 device is configured to operate in the POS-PHY Level 3
Mode, then this signal will be tri-stated until two RxPClk cycles following the
assertion of a valid address on the Receive POS-PHY Address bus input pins
(e.g., if the contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0],
match that which have been assigned to this particular Receive POS-PHY Inter-
face block). Afterwards, this output pin will be driven either "high" or "low"
depending upon the current fill status of the RxFIFO.
A14
RxUClkO/
RxPClkO
O
Receive UTOPIA Interface Clock/Receive POS-PHY Interface Clock Out-
put:
This clock output signal is derived from an internal PLL.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT79L73IB | 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設備/調整器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L73IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
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