Rev. 1.01 6.9 Configuring the XRT8001 WAN Clock into the “Forward/Slave” Mode. The user can configure the XRT8001 WAN Clock to opera" />
參數(shù)資料
型號: XRT8001ID-F
廠商: Exar Corporation
文件頁數(shù): 25/48頁
文件大?。?/td> 0K
描述: IC WAN T1/E1 DUAL 18SOIC
標(biāo)準(zhǔn)包裝: 20
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(wǎng)(WAN),T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 16.384kHz
電源電壓: 3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 管件
其它名稱: 1016-1358-5
XRT8001
31
Rev. 1.01
6.9 Configuring the XRT8001 WAN Clock into the
“Forward/Slave” Mode.
The user can configure the XRT8001 WAN Clock to
operate in the “Forward/Slave Mode” by executing the
following steps:
Step 1 – Configure the XRT8001 to operate in the
“SLAVE” Mode by pulling the MSB input pin (pin 8) to
GND.
Step 2 – Refer to Table 2B and write the value that
corresponds to the desired "Forward/Slave" Mode into
Bits D[4:1] within Command Register CR0.
Step 3 – Define the values for L, for the CLK1 output
by writing the appropriate value into the CR2 register.
This is achieved by writing the value “L – 1” into this
register.
Notes:
1.
For example, if the user writes “00000” into this regis-
ter, then the XRT8001 device will output a 64kHz
signal via the CLK1 output pin.
2.
If the user intends to output data via CLK1, then he/she
must ensure that the PL1EN bit-field within Command
Register CR0 is set to “1”.
Figure 18. Illustration of the XRT8001 WAN Clock operating in the
“Forward/Slave" Mode
Step 4- Define the value for L, for the CLK2 output
by writing the appropriate value into the CR3 regis-
ter. This is achieved by writing the value “L – 1”
into this register.
Note: If the user intends to output data via CLK2, then he/
she must ensure that the PL2EN bit-field within Command
Register CR1 is set to “1”.
Step 5 – Set the CLK1EN and CLK2EN bit-fields,
within Command Register CR4 to 1 in order to
enable the output drivers for CLK1 and CLK2, as
illustrated below.
XRT8001
WAN Clock
FIN
CLK1
CLK2
8kHz
L x 56kHz
to
L x 64kHz
1 < L < 32
L x 56kHz
to
L x 64kHz
1 < L < 32
Command Register CR4
D4
D3
D2
D1
D0
SYNCEN
CLK1EN
CLK2EN
X
x
1
0
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