Rev. 1.01 AC ELECTRICAL CHARACTERISTICS (See Figure 4.) Symbol Parameter Min. Typ. Max. Units Conditions t1 Input Frequency 0.008 32." />
參數(shù)資料
型號: XRT8001ID-F
廠商: Exar Corporation
文件頁數(shù): 45/48頁
文件大?。?/td> 0K
描述: IC WAN T1/E1 DUAL 18SOIC
標(biāo)準(zhǔn)包裝: 20
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(wǎng)(WAN),T1/E1
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 16.384kHz
電源電壓: 3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 管件
其它名稱: 1016-1358-5
XRT8001
6
Rev. 1.01
AC ELECTRICAL CHARACTERISTICS (See Figure 4.)
Symbol
Parameter
Min.
Typ.
Max. Units
Conditions
t1
Input Frequency
0.008
32.7
MHz
3.3V
0.008
32.7
MHz
5V
t2
Minimum Input Signal “High” to
12
ns
“Low” Duration
t3
Output Frequency
56
16,384
kHz
t61
Duty Cycle
47.5
50
52.5
%
VCC/2 switch point, 30pF Load
t74
Jitter Added 8kHz – 40kHz
0.01
0.02
UI
3.3V, Output = 1.544MHz (0.025 UI)3
0.01
0.02
UI
5V, Output = 1.544MHz (0.025 UI)3
t74
Jitter Added 10Hz – 40kHz
0.03
UI
3.3V, Output = 1.544MHz (0.025 UI)3
0.03
UI
5V, Output = 1.544MHz (0.025 UI)3
t74
Broadband Jitter
0.03
0.05
UI
3.3V, Output = 1.544MHz (0.05 UI)3
0.035 0.05
UI
5V, Output = 1.544MHz (0.05 UI)3
t74
Jitter Added 20Hz – 100kHz
0.07
UI
3.3V, Output = 2.048MHz (1.5 UI)3
0.01
0.07
UI
5V, Output = 2.048MHz (1.5 UI)3
t74
Jitter Added 18kHz – 100kHz
0.03
UI
3.3V, Output = 2.048MHz (0.2 UI)3
0.007 0.03
UI
5V, Output = 2.048MHz (0.2 UI)3
t8
Capture Time
40
ms
3.3V
40
ms
5V
t9
Clock Output Rise Time
10ns
ns
30pF load measured at 20/80%
t10
Clock Output Fall Time
10ns
ns
30pF load measured at 20/80%
t112
SYNC Output Signal Duty Cycle
40
60
%
VCC/2 switch point
t12
SYNC Ouput Signal + Cycle
t13
SYNC Output Signal – Cycle
t14
Delay Time between the rising
t-20
t+20
ns
See Table 8 for values of “t”
edge of of SYNC and the Rising
edge of CLK1 and CLK2
t21
CSB Low to Rising Edge of SCLK
50
ns
Setup Time
t22
CSB High to Rising Edge of SCLK
20
ns
Hold Time
t23
SDI to Rising Edge of SCLK Setup Time
50
ns
t24
SDI to Rising Edge of SCLK Hold Time
50
ns
t25
SCLK “Low” Time
240
ns
t26
SCLK “High” Time
240
ns
t27
SCLK Period
500
ns
t28
CSB Low to Rising Edge of SCLK
50
ns
Hold Time
t29
CSB “Inactive” Time
250
ns
t30
Falling Edge of SCLK to SDO Valid Time
200
ns
t31
Falling Edge of SCLK to SDO Invalid Time
100
ns
t32
Falling Edge of SCLK, or rising edge
100
ns
of CSB to High Z
t33
Rise/Fall time of SDO Output
40
ns
PW
MIN
F
IN Duty Cycle
12
ns
Notes:
1
2
3
Specifications from AT&T Publication 62411 and ITU-T
Recommendations G-823 (for 1.544MHz and (2.048MHz).
4
t7 is guaranteed by characterization, not tested.
t6 =
t4
(t4 + t5)
t11 =
t12
(t12 + t13)
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