參數(shù)資料
型號： XRT83SL314IB
廠商： Exar Corporation
文件頁數(shù)： 19/83頁
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝： 27
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 14/14
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 304-LBGA
供應(yīng)商設(shè)備封裝： 304-TBGA（31x31）
包裝： 托盤
XRT83SL314
xr
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
23
In T1 mode, RLOS is declared if an incoming signal has no transitions over a period of 175 +/-75 contiguous
pulse intervals. However, the XRT83SL314 LIU has a built in analog RLOS so that the user can be notified
when the amplitude of the incoming signal has been attenuated -9dB below the equalizer gain setting. For
example:
In T1 or E1 short haul mode, the equalizer gain setting is 15dB.
Once the input reaches an
amplitude of -24dB below nominal, the LIU will declare RLOS. The RLOS circuitry clears when the input
reaches +3dB relative to where it was declared. This +3dB value is a pre-determined hysteresis so that
transients will not cause the RLOS to clear. In E1 mode, RLOS is declared if an incoming signal has no
transitions for N consecutive pulse intervals, where 10
≤N≤255. According to G.775, no transitions in E1 mode
is defined between -9dB and -35dB below nominal. Figure 14 is a simplified block diagram of the analog
RLOS function. Table 6 summarizes the analog RLOS values for the different equalizer gain settings.
FIGURE 14. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1
NOTE: For programming the equalizer gain setting on a per channel basis, see the microprocessor register map for details.
2.6.3.2
EXLOS (Extended Loss of Signal)
By enabling the extended loss of signal by programming the appropriate channel register, the digital RLOS is
extended to count 4,096 consecutive zeros before declaring RLOS in T1 and E1 mode. By default, EXLOS is
disabled and RLOS operates in normal mode.
2.6.3.3
AIS (Alarm Indication Signal)
The XRT83SL314 adheres to the ITU-T G.775 specification for an all ones pattern. The alarm indication signal
is set to "1" if an all ones pattern (at least 99.9% ones density) is present for T, where T is 3ms to 75ms in T1
mode. AIS will clear when the ones density is not met within the same time period T. In E1 mode, the AIS is
set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming signal
has 3 or more zeros in the 512-bit window.
TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1
GAIN SETTING
DECLARE
CLEAR
15dB (Short Haul Mode)
-24dB
-21dB
29dB (Monitoring Gain Mode)
-38dB
-35dB
Normalized up to EQC[4:0] Setting
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
Normalized up to EQC[4:0] Setting
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