XRT83SL314
xr
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
59
NOTE: Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the
global register 0xE0h). The status registers are reset upon read (RUR).
TABLE 31: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-13 (0X06H-0XD6H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
EQFLAGS
Equalizer Attenuation Flag Status
0 = No change
1 = Change in status occurred
RUR
0
D6
DMOIS
Digital Monitor Output Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV/OFIS
Line Code Violation / Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
NLCDIS
Network Loop Code Detection Status
0 = No change
1 = Change in status occurred
RUR
0
D2
AISDIS
Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D1
RLOSIS
Receiver Loss of Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D0
QRPDIS
Quasi Random Pattern Detection Status
0 = No change
1 = Change in status occurred
RUR
0