參數(shù)資料
型號: XRT83SL38IB
廠商: Exar Corporation
文件頁數(shù): 10/88頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SL38
16
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
CLKSEL0
CLKSEL1
CLKSEL2
A8
B8
C8
I
Clock Select inputs for Master Clock Synthesizer - Hardware mode
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
used to generate a master clock from an external accurate clock source according to
the table below.
In Hardware mode, the MCLKRATE control signal is generated from the state of
EQC[4:0] inputs.
In Host mode, the state of these pins are ignored and the master frequency PLL is con-
trolled by the corresponding interface bits. See
Table 36 register address 10000001
NOTE: These pins are internally pulled “Low” with a 50k
Ω resistor.
SIGNAL
NAME
LEAD #TYPE
DESCRIPTION
204 8
154 4
MCLK E1
kH z
8
16
56
8
56
64
128
256
128
2048
1544
M C LKT1
kH z
1544
X
1544
X
2 048
1 544
2 048
CLKOUT/
kH z
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
0
1
CLKS EL0
0
1
0
1
0
1
0
CLKSEL1
1
0
1
0
1
0
CLK SEL2
0
1
0
1
0
1
0
154 4
204 8
X
2 048
1 544
0
1
0
1
M C LKR ATE
1
0
1
0
1
0
1
0
1
0
1
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