參數(shù)資料
型號(hào): XRT83SL38IB
廠商: Exar Corporation
文件頁(yè)數(shù): 16/88頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤(pán)
XRT83SL38
21
REV. 1.0.2
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TVDD_0
TVDD_1
TVDD_2
TVDD_3
TVDD_4
TVDD_5
TVDD_6
TVDD_7
E4
F4
F16
E17
R4
P1
N15
P15
****
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _0
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _1
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _2
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _3
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _4
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _5
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _6
Transmitter Analog Positive Supply (3.3V + 5%) for Channel _7
RVDD_0
RVDD_1
RVDD_2
RVDD_3
RVDD_4
RVDD_5
RVDD_6
RVDD_7
C2
E5
G16
D16
V2
N3
N17
U18
****
Receiver Analog Positive Supply (3.3V± 5%) for Channel _0
Receiver Analog Positive Supply (3.3V± 5%) for Channel _1
Receiver Analog Positive Supply (3.3V± 5%) for Channel _2
Receiver Analog Positive Supply (3.3V± 5%) for Channel _3
Receiver Analog Positive Supply (3.3V± 5%) for Channel _4
Receiver Analog Positive Supply (3.3V± 5%) for Channel _5
Receiver Analog Positive Supply (3.3V± 5%) for Channel _6
Receiver Analog Positive Supply (3.3V± 5%) for Channel _7
RGND_0
RGND_1
RGND_2
RGND_3
RGND_4
RGND_5
RGND_6
RGND_7
D2
G3
G17
D17
T2
M2
M17
R17
****
Receiver Analog Ground for Channel_0
Receiver Analog Ground for Channel_1
Receiver Analog Ground for Channel_2
Receiver Analog Ground for Channel_3
Receiver Analog Ground for Channel_4
Receiver Analog Ground for Channel_5
Receiver Analog Ground for Channel_6
Receiver Analog Ground for Channel_7
AVDD Bias
VDDPLL_1
VDDPLL_2
K17
J3
J2
****
Analog Positive Supply (3.3V± 5%)
Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
AGND Bias
GNDPLL_1
GNDPLL_2
J17
K3
L4
****
Analog Ground
Analog Ground for Master Clock Synthesizer PLL
DVDD_DRV
DVDD_PRE
DVDD
μP
DVDD_PRE
DVDD_DRV
DVDD
R9
U10
K18
D10
K15
A9
****
Digital Positive Supply (3.3V± 5%)
DGND_PRE
DGND_DRV
DGND P
DGND
DGND_DRV
DGND_PRE
R8
T9
H17
B9
D8
C9
****
Digital Ground
SIGNAL NAME
LEAD #TYPE
DESCRIPTION
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