TABLE
參數(shù)資料
型號： XRT86VL38IB
廠商： Exar Corporation
文件頁數(shù)： 157/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝： 40
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 420-BBGA
供應(yīng)商設(shè)備封裝： 420-PBGA
包裝： 托盤
XRT86VL38
91
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 80: BLOCK INTERRUPT STATUS REGISTER (BISR)
HEX ADDRESS: 0XnB00
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
For E1 mode only
6
LBCODE
RO
0
Loopback Code Block Interrupt Status
This bit indicates whether or not the Loopback Code block has an
interrupt request awaiting service.
0 - Indicates no outstanding Loopback Code Block interrupt request
is awaiting service
1 - Indicates the Loopback Code block has an interrupt request
awaiting service. Interrupt Service routine should branch to the inter-
rupt source and read the Loopback Code Interrupt Status register
(address 0xnB0A) to clear the interrupt
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the Loopback Code Interrupt Status
Register.
5
RxClkLOS
RO
0
Loss of Recovered Clock Interrupt Status
This bit indicates whether or not the framer has experienced a Loss
of Recovered Clock interrupt since last read of this register.
0 = Indicates Loss of Recovered Clock interrupt has not occurred
since last read of this register
1 = Indicates Loss of Recovered Clock interrupt has occurred since
last read of this register.
NOTE: This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4
ONESEC
RO
0
One Second Interrupt Status
This bit indicates whether or not the framer has experienced a One
Second interrupt since the last read of this register.
0 = Indicates One Second interrupt has not occurred since the last
read of this register
1 = Indicates One Second interrupt has occurred since the last read
of this register
3
HDLC
RO
0
HDLC Block Interrupt Status
This bit indicates whether or not the HDLC block has any interrupt
request awaiting service.
0 = Indicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicates HDLC Block has an interrupt request awaiting service.
Interrupt Service routine should branch to the interrupt source and
read the corresponding Data LInk Status Registers (address
0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the
interrupt.
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generated the interrupt.
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