TABLE
參數(shù)資料
型號： XRT86VL38IB
廠商： Exar Corporation
文件頁數(shù)： 55/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝： 40
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 420-BBGA
供應(yīng)商設(shè)備封裝： 420-PBGA
包裝： 托盤
XRT86VL38
143
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 117: LIU CHANNEL CONTROL ARBITRARY REGISTER 1 (LIUCCAR1)
HEX ADDRESS: 0X0FN8
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg1
R/W
0
Arbitrary Transmit Pulse Shape, Segment 1:
These seven bits form the first of the eight segments of the transmit
shape pulse when the XRT86VL38 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
TABLE 118: LIU CHANNEL CONTROL ARBITRARY REGISTER 2 (LIUCCAR2)
HEX ADDRESS: 0X0FN9
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg2
R/W
0
Arbitrary Transmit Pulse Shape, Segment 2
These seven bits form the second of the eight segments of the
transmit shape pulse when the XRT86VL38 is configured in “Arbi-
trary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
TABLE 119: LIU CHANNEL CONTROL ARBITRARY REGISTER 3 (LIUCCAR3)
HEX ADDRESS: 0X0FNA
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_seg3
R/W
0
Arbitrary Transmit Pulse Shape, Segment 3
These seven bits form the third of the eight segments of the transmit
shape pulse when the XRT86VL38 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
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