TABLE
參數(shù)資料
型號： XRT86VL38IB
廠商： Exar Corporation
文件頁數(shù)： 159/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 420BG
標準包裝： 40
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 420-BBGA
供應(yīng)商設(shè)備封裝： 420-PBGA
包裝： 托盤
XRT86VL38
93
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 81: BLOCK INTERRUPT ENABLE REGISTER (BIER)
HEX ADDRESS: 0XnB01
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
For E1 mode only
6
LBCODE_ENB
R/W
0
Loopback Code Block interrupt enable
This bit permits the user to either enable or disable the Loopback
Code Interrupt Block for interrupt generation.
Writing a “0” to this register bit will disable the Loopback Code Block
for interrupt generation, all Loopback Code interrupts will be dis-
abled for interrupt generation.
If the user writes a “1” to this register bit, the Loopback Code Inter-
rupts at the “Block Level” will be enabled. However, the individual
Loopback Code interrupts at the “Source Level” still need to be
enabled to in order to generate that particular interrupt to the inter-
rupt pin.
0 - Disables all Loopback Code Interrupt Block interrupt within the
device.
1 - Enables the Loopback Code interrupt at the “Block-Level”.
5
RXCLKLOSS
R/W
0
Loss of Recovered Clock Interrupt Enable
This bit permits the user to either enable or disable the Loss of
Recovered Clock Interrupt for interrupt generation.
0 - Disables the Loss of Recovered Clock Interrupt within the device.
1 - Enables the Loss of Recovered Clock interrupt at the “Source-
Level”.
4
ONESEC_ENB
R/W
0
One Second Interrupt Enable
This bit permits the user to either enable or disable the One Second
Interrupt for interrupt generation.
0 - Disables the One Second Interrupt within the device.
1 - Enables the One Second interrupt at the “Source-Level”.
3
HDLC_ENB
R/W
0
HDLC Block Interrupt Enable
This bit permits the user to either enable or disable the HDLC Block
for interrupt generation.
Writing a “0” to this register bit will disable the HDLC Block for inter-
rupt generation, all HDLC interrupts will be disabled for interrupt
generation.
If the user writes a “1” to this register bit, the HDLC Block interrupt at
the “Block Level” will be enabled. However, the individual HDLC
interrupts at the “Source Level” still need to be enabled in order to
generate that particular interrupt to the interrupt pin.
0 - Disables all SA6 Block interrupt within the device.
1 - Enables the SA6 interrupt at the “Block-Level”.
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