參數(shù)資料
型號： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁數(shù)： 24/61頁
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標準包裝： 90
控制器類型： T1/E1/J1 調幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應商設備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
27
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.3
REQ0
T19
N16
O
8
DMA Cycle Request Output—DMA Controller 0 (Write):
These output pins are used to indicate that DMA transfers
(Write) are requested by the T1/E1 Framer.
On the transmit side (i.e., To transmit data from external
DMA controller to HDLC buffers within the XRT86VX38),
DMA transfers are only requested when the transmit buffer
status bits indicate that there is space for a complete mes-
sage or cell.
The DMA Write cycle starts by T1/E1 Framer asserting the
DMA Request (REQ0) ‘low’, then the external DMA control-
ler should drive the DMA Acknowledge (ACK0) ‘low’ to indi-
cate that it is ready to start the transfer. The external DMA
controller should place new data on the Microprocessor
data bus each time the Write Signal is Strobed low if the
WR is configured as a Write Strobe. If WR is configured as
a direction signal, then the external DMA controller would
place new data on the Microprocessor data bus each time
the Read Signal (RD) is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
at least one of the Transmit HDLC buffers are empty and
can receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when
the HDLC buffer can no longer receive another HDLC mes-
sage.
REQ1
R16
O
8
DMA Cycle Request Output—DMA Controller 1 (Read):
These output pins are used to indicate that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the receive side (i.e., To transmit data from HDLC buff-
ers within the XRT86VX38 to external DMA Controller),
DMA transfers are only requested when the receive buffer
contains a complete message or cell.
The DMA Read cycle starts by T1/E1 Framer asserting the
DMA Request (REQ1) ‘low’, then the external DMA control-
ler should drive the DMA Acknowledge (ACK1) ‘low’ to indi-
cate that it is ready to receive the data. The T1/E1 Framer
should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is con-
figured as a Read Strobe. If RD is configured as a direction
signal, then the T1/E1 Framer would place new data on the
Microprocessor data bus each time the Write Signal (WR)
is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
one of the Receive HDLC buffer contains a complete
HDLC message that needs to be read by the C/P.
The Framer negates this output pin (toggles it “High”) when
the Receive HDLC buffers are depleted.
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
DESCRIPTION
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