參數(shù)資料
型號： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁數(shù)： 9/61頁
文件大小： 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標準包裝： 90
控制器類型： T1/E1/J1 調幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應商設備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
14
REV. 1.0.3
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxSERCLK0/
TxLINECLK0
TxSERCLK1/
TxLINECLK1
TxSERCLK2/
TxLINECLK2
TxSERCLK3/
TxLINECLK3
TxSERCLK4/
TxLINECLK4
TxSERCLK5/
TxLINECLK5
TxSERCLK6/
TxLINECLK6
TxSERCLK7/
TxLINECLK7
B11
D14
C17
F18
V17
T11
W8
U5
D10
B13
B15
E16
T14
N10
T7
P6
I/O
12
Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock
(TxSERCLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn:
This clock signal is used by the transmit serial interface to
latch the contents on the TxSERn pins into the T1/E1 framer
on the rising edge of the TxSERCLKn. These pins can be con-
figured as input or output as described below.
When TxSERCLKn is configured as Input:
These pins will be inputs if the TxSERCLK is chosen as the
timing source for the transmit framer. Users must provide a
1.544MHz clock rate to this input pin for T1 mode of operation,
and 2.048MHz clock rate in E1 mode.
When TxSERCLKn is configured as Output:
These pins will be outputs if either the recovered line clock or
the MCLK PLL is chosen as the timing source for the T1/E1
transmit framer. The transmit framer will output a 1.544MHz
clock rate in T1 mode of operation, and a 2.048MHz clock rate
in E1 mode.
DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as
INPUT ONLY
In this mode, TxSERCLK is an optional clock signal input
which is used as the timing source for the transmit line inter-
face, and is only required if TxSERCLK is chosen as the tim-
ing source for the transmit framer. If TxSERCLK is chosen as
the timing source, system equipment should provide
1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the
TxSERCLKn pins on each channel. TxSERCLK is not
required if either the recovered clock or MCLK PLL is chosen
as the timing source of the device.
High speed or multiplexed data is latched into the device using
the TxMSYNC/TxINCLK high-speed clock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In this mode, TxSERCLKn is used as the transmit line clock
(TxLINECLK) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP,
4.096MHz,
8.192MHz,
16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE:
These 8 pins are internally pulled “High” for each
channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE(MA)
DESCRIPTION
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