參數(shù)資料
型號: XRT91L30
廠商: Exar Corporation
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器
文件頁數(shù): 21/40頁
文件大小: 387K
代理商: XRT91L30
xr
REV. P1.0.8
PRELIMINARY
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30
19
2.8
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel
data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered
clock. A simplified block diagram is shown in Figure 9.
Receive Parallel Output Interface
2.9
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS
condition to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping
LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin from the optical module to
force an LOS and mute the parallel receiver outputs as well.
Disable Parallel Receive Data Output Upon LOS
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
SONET Framer/ASIC
XRT91L30
STS-12/STM-4
or
STS-3/STM-1
Transceiver
RXPCLKO
RXDO[7:0]
8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L30_0611 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
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