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參數(shù)資料
| 型號(hào)： | XRT91L30 |
| 廠商： | Exar Corporation |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 387K |
| 代理商： | XRT91L30 |
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xr
REV. P1.0.8
PRELIMINARY
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30
5
CDRREFSEL
LVTTL
I
60
Clock and Data Recover Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
based on the table below.
"Low" = CDR uses CMU’s reference clock
"High" = CDR reference clock from CDRAUXREFCLK
N
OTE
:
CDRAUXREFCLK requires accuracy of 77.76 MHz
+/- 500ppm.
LOOPTIME
LVTTL
I
2
Loop Timing Mode
When the loop timing mode is activated the external reference
clock to the input of the Retimer is replaced with the high-speed
recovered receive clock from the CDR.
"Low" = Disabled
"High" = Loop timing Activated
CDRDIS
LVTTL
I
12
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit.
Received serial data bypasses the integrated CDR block.
RXINP/N is then sampled on the rising edge of externally
recovered differential clock XRXCLKIP/N coming from the opti-
cal module.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled and Bypassed
PIO_CTRL
LVTTL
I
48
Transmit Parallel Clock Directional Control
Transmit Parallel Clock Output Operation
If this pin is asserted "High", TXPCLK_IO is a parallel bus clock
output. Data on the TXDI[7:0] must be synchronously applied
prior to the sampling by the PISO at the rising edge of
TXPCLK_IO clock output driven by the XRT91L30.
Alternate Transmit Parallel Clock Input Operation
Asserting this control pin "Low" or if left unconnected, it config-
ures TXPCLK_IO to serve as a parallel bus clock input rather
than a parallel bus clock output and permits the XRT91L30 to
accept the external clock input. Data on the TXDI[7:0] is then
sampled at the rising edge of the TXPCLK_IO clock input
driven by the framer/mapper device.
"Low" = TXPCLK_IO is a Parallel Clock Input.
"High" = TXPCLK_IO is a Parallel Clock Output.
N
OTE
:
Parallel Clock Input operation has the advantage of
permitting the framer/mapper device timing to be
synchronized with the transceiver transmitter timing.
This pin is provided with an internal pull-down.
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
CDRREFSEL
STS12/
STS3
CDRAUXREFCLK
F
REQUENCY
D
ATA
R
ATE
0
CDR uses CMU’s reference clock
(see CMUFREQSEL pin)
1
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
1
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L31 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32IQ-F | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L80 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L30_0611 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30_10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS12-STM4 OR STS3-STM1 SONET-SDH Transceiver |
| XRT91L306 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30ES | 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L30IQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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