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參數(shù)資料
| 型號(hào)： | XRT91L31IQ |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT91L31IQ |
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XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
18
During RLOOPS operation, the 91L31 mutes the RLOOPS data going to Tx output upon detection of DLOS
while DLOSDIS is not enabled. During RLOOPS operation, the 91L31 also mutes the RLOOPS data going to
Tx output while the LOSEXT input is set to a “LOW” state. Note that the DLOSDIS control pin has no impact
on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting as a result of DLOS detection.
Also, note that the muting function only impacts the RLOOPS data going to Tx output, and the CDR clock
output & RLOOPS clock going to Tx block shall remain active (see Figure 7.)
2.6
SONET Frame Boundary Detection and Byte Alignment Recovery
A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1
(0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control
of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held
"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing
pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-to-
parallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for
output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse
(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern
matching the framing pattern is detected on the incoming data stream. While in the pattern search and
detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte
clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/
STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once
the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF
input pin should be de-asserted by the SONET Framer to disable the XRT91L31 frame search process from
trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L31’s framing pattern
detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will
lock to the detected location and will remain locked to that location found when detection was previously
enabled.
2.7
Receive Serial Input to Parallel Output (SIPO)
During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps
parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/
STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO
bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is
shown in Figure 8. XRT91L31 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO
b
0
0
b
0
1
b
0
2
b
0
3
b
n
0
b
n
1
b
n
2
b
n
3
b
n+
0
b
n+
1
b
n+
2
b
n+
3
b
7
0
b
7
1
b
7
2
b
7
3
8-bit Parallel LVTTL Output Data
RXDO0
RXDO7
RXDO
n+
RXDOn
RXIP/N
RXPCLKO
b
3
0 b
2
0 b
1
0 b
0
0
b
7
0 b
6
0 b
5
0 b
4
0
b
3
3 b
2
3 b
1
3
b
4
3
b
5
3
b
6
3
b
7
3
S
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L32 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32IQ-F | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L80 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80_0507 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L31IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L31IQ-F | 制造商:Exar Corporation 功能描述:SONET Transceiver IC |
| XRT91L31IQTR | 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L31IQTR-F | 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
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