參數(shù)資料
型號(hào)： XRT91L31IQ
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-64
文件頁(yè)數(shù)： 4/41頁(yè)
文件大?。?/td> 356K
代理商： XRT91L31IQ
XRT91L31
REV. 1.0.2
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L31...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
F
IGURE
2. 64 QFP P
IN
O
UT
OF
THE
XRT91L31 (T
OP
V
IEW
)............................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS ..........................................................................................................4
.....................................................................................................................................................................4
H
ARDWARE
C
ONTROL
....................................................................................................................................4
T
RANSMITTER
S
ECTION
..................................................................................................................................7
R
ECEIVER
S
ECTION
........................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................10
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
T
ABLE
1: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL
OR
S
INGLE
-E
NDED
) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
T
ABLE
2: D
ATA
INGRESS
TO
DATA
EGRESS
LATENCY
....................................................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
F
IGURE
4. R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
D
IAGRAM
.......................................................................................... 14
T
ABLE
3: R
ECEIVE
H
IGH
-
SPEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ............................................................. 14
T
ABLE
4: R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
5: C
LOCK
D
ATA
R
ECOVERY
UNIT
REFERENCE
CLOCK
SETTINGS
............................................................................................ 15
T
ABLE
6: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 16
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16
F
IGURE
5. I
NTERNAL
C
LOCK
AND
D
ATA
R
ECOVERY
B
YPASS
............................................................................................................ 16
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 17
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 17
2.5 LOSS OF SIGNAL .......................................................................................................................................... 17
F
IGURE
7. LOS D
ECLARATION
CIRCUIT
........................................................................................................................................... 17
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 18
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 18
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 18
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 19
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 19
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 19
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 20
F
IGURE
10. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
............................................................................................................................ 20
T
ABLE
7: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 20
T
ABLE
8: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 20
T
ABLE
9: PECL
AND
TTL R
ECEIVE
O
UTPUTS
T
IMING
S
PECIFICATION
.............................................................................................. 21
3.0 TRANSMIT SECTION ..........................................................................................................................22
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 22
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 22
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 23
F
IGURE
12. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 23
T
ABLE
10: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 23
T
ABLE
11: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 23
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 24
F
IGURE
13. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
(P
ARALLEL
C
LOCK
I
NPUT
O
PTION
)...................................... 24
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 24
F
IGURE
14. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
............................................................................................................ 24
T
ABLE
12: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ...................................................... 25
T
ABLE
13: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
). ....................................................... 25
相關(guān)PDF資料
PDF描述
XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L32IQ-F STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80_0507 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L31IQ-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT91L31IQ-F 制造商:Exar Corporation 功能描述:SONET Transceiver IC
XRT91L31IQTR 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L31IQTR-F 功能描述:總線收發(fā)器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L32 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
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