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參數資料
| 型號： | XRT91L32IQ-F |
| 廠商： | EXAR CORP |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100 |
| 文件頁數： | 25/37頁 |
| 文件大?。?/td> | 417K |
| 代理商： | XRT91L32IQ-F |
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xr
REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
23
3.3
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or
155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The
PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit
from TXDI6, and so on as shown in Figure 13.
Transmit Parallel Input to Serial Output (PISO)
3.4
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK reference clock is used, the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 1, on page 11 shows the CMU reference clock frequency settings. Table 12
specifies the Clock Multiplier Unit’s requirements for the reference clock.
T
ABLE
12: C
LOCK
M
ULTIPLIER
U
NIT
REQUIREMETNS
FOR
REFERENCE
CLOCK
Clock Multiplier Unit (CMU) and Re-Timer
F
IGURE
13. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
40
60
%
REF
JIT
Reference clock jitter (rms) with 19.44 MHz reference
1
5
ps
REF
JIT
Reference clock jitter (rms) with 77.76 MHz reference
1
13
ps
REF
TOL
Reference clock frequency tolerance
2
-20
+20
ppm
ECLK
JIT
STS-3/STM-1 Electrical Clock output jitter (rms) with 19.44 MHz reference
1
mUI
rms
ECLK
JIT
STS-12/STM-4 Electrical Clock output jitter (rms) with 19.44 MHz reference
5
mUI
rms
ECLK
JIT
STS-3/STM-1 Electrical Clock output jitter (rms) with 77.76 MHz reference
2
mUI
rms
ECLK
JIT
STS-12/STM-4 Electrical Clock output jitter (rms) with 77.76 MHz reference
4
mUI
rms
b
0
0
b
0
1
b
0
2
b
0
3
b
0
4
b
0
5
b
0
6
b
0
7
b
n
0
b
n
1
b
n
2
b
n
3
b
n
4
b
n
5
b
n
6
b
n
7
b
n+
0
b
n+
1
b
n+
2
b
n+
3
b
n+
4
b
n+
5
b
n+
6
b
n+
7
b
7
0
b
7
1
b
7
2
b
7
3
b
7
4
b
7
5
b
7
6
b
7
7
8-bit Parallel LVTTL Input Data
TXDI0
TXDI7
TXDI
n+
TXDIn
TXOP/N
TXPCLK_IO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
b
4
0
b
5
0
b
6
0
b
7
0
b
2
0
b
3
0
b
4
7
b
5
7
b
6
7
b
7
7
b
0
7
b
1
7
b
2
7
b
3
7
P
time (0)
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| XRT91L80IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT91L32IQTR | 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT91L32IQTR-F | 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT91L33 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT |
| XRT91L33AIG-F | 制造商:Exar Corporation 功能描述:CDR 155.52Mbps/622.08Mbps SONET/SDH 20-Pin TSSOP |
| XRT91L33ES | 功能描述:界面開發(fā)工具 Eval System for XRT91L33 Series RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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