參數(shù)資料
型號(hào)： XRT91L80
廠商： Exar Corporation
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666 Gbps的STS-48/STM-16的SONET / SDH收發(fā)器
文件頁(yè)數(shù)： 26/45頁(yè)
文件大小： 359K
代理商： XRT91L80
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.1.0
24
4.0
DIAGNOSTIC FEATURES
4.1
The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is
activated, the high-speed serial receive data from RXIP/N is presented at the high-speed transmit output
TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input
of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to
parallel data and presented at the low-speed receive parallel interface RXDO[3:0]P/N. The recovered receive
clock is also divided by 4 and presented at the low-speed clock output RXPCLKOP/N to synchronize the
transfer of the 4-bit received parallel data. A simplified block diagram of serial remote loopback is shown in
Figure 16.
Serial Remote Loopback
4.2
RLOOPP controls a more comprehensive version of remote loop-back that can also be used in conjunction
with the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is
processed by the CDR, and is sent through the serial to parallel converter. At this point, the 4-bit parallel data
and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also
employed, the received clock is divided down in frequency and presented to the input of the integrated phase/
frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_INP/N inputs.
With the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL
asserted, the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime
the transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset
using FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified
block diagram of parallel remote loopback is shown in Figure 17.
Parallel Remote Loopback
F
IGURE
16. S
ERIAL
R
EMOTE
L
OOPBACK
F
IGURE
17. P
ARALLEL
R
EMOTE
L
OOPBACK
PISO
Re-Timer
CML
Output Drivers
FIFO
SIPO
CDR
CML
Input Drivers
Serial Remote Loopback
RX Parallel Output
TX Serial Output
RX Serial Input
PISO
Re-Timer
CML
Output Drivers
FIFO
SIPO
CDR
CML
Input Drivers
Parallel Remote Loopback
RX Parallel Output
TX Serial Output
RX Serial Input
相關(guān)PDF資料
PDF描述
XRT91L80_0507 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L80_0507 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
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