參數(shù)資料
型號: XWM8728EDS
廠商: Wolfson Microelectronics
英文描述: 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support
中文描述: 24位,192kHz立體聲DAC,具有音量控制和渠務署支持
文件頁數(shù): 18/28頁
文件大?。?/td> 266K
代理商: XWM8728EDS
WM8728
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
18
REGISTER MAP
WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.
Using either 2-wire or 3-wire serial control mode as shown in Figure 14 and Figure 15.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
M0
0
0
0
0
0
0
0
UPDATEL
LAT7
LAT6
LAT5
LAT4
LAT3
LAT2
LAT1
LAT0
M1
0
0
0
0
0
0
1
UPDATER
RAT7
RAT6
RAT5
RAT4
RAT3
RAT2
RAT1
RAT0
M2
0
0
0
0
0
1
0
0
0
0
IW2
IW1
IW0
PWDN
EEMPH
MUT
M3
0
0
0
0
0
1
1
IZD
0
0
BCP
REV
0
ATC
LRP
I
2
S
ADDRESS
DATA
Table 6 Mapping of Program Registers
REGISTER
ADDRESS
(A3,A2,A1,A0)
0000
DACL
Attenuation
BITS
NAME
DEFAULT
DESCRIPTION
[7:0]
8
LAT[7:0]
UPDATEL
11111111 (0dB)
0
Attenuation data for left channel in 0.5dB steps, see Table 9
Attenuation data load control for left channel.
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on both channels.
Attenuation data for right channel in 0.5dB steps, see Table 9
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on both channels.
Left and right DACs soft mute control.
0: No mute
1: Mute
De-emphasis control.
0: De-emphasis off
1: De-emphasis on
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Audio data format select, see Table 14
Audio data format select, see Table 14
Polarity select for LRCIN/DSP mode select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
Attenuator Control.
0: All DACs use attenuation as programmed.
1: Right channel DACs use corresponding left DAC
attenuation
Output phase reverse.
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
Infinite ZERO detection circuit control and automute control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
[7:0]
8
RAT[7:0]
UPDATER
11111111 (0dB)
0
0001
DACR
Attenuation
0
MUT
0
1
DEEMPH
0
2
PWDN
0
0010
DAC Control
[5:3]
0
1
IW[2:0]
I
2
S
LRP
0
0
0
2
ATC
0
4
5
REV
BCP
0
0
0011
Interface
Control
8
IZD
0
Table 7 Register Bit Descriptions
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