參數(shù)資料
型號(hào)： XWM8728EDS
廠商： Wolfson Microelectronics
英文描述： 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support
中文描述： 24位，192kHz立體聲DAC，具有音量控制和渠務(wù)署支持
文件頁數(shù)： 21/28頁
文件大?。?/td> 266K
代理商： XWM8728EDS
WM8728
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WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
21
SELECTION OF LRCIN POLARITY
In left justified, right justified or I
2
S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 7,
Figure 8 and Figure 9. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
0011
Interface Control
BIT
1
LABEL
LRP
DEFAULT
0
DESCRIPTION
LRCIN Polarity (normal)
0 : normal LRCIN polarity
1: inverted LRCIN polarity
Table 15 LRCIN Polarity Control
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure
10 and Figure 11.
REGISTER ADDRESS
0011
Interface Control
BIT
1
LABEL
LRP
DEFAULT
0
DESCRIPTION
DSP Format (DSP modes)
0 : Late DSP mode
1: Early DSP mode
Table 16 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN
rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left
and right channel DACs from the next audio input sample. No update to the attenuation registers
is required for ATC to take effect.
REGISTER ADDRESS
0011
Interface Control
BIT
2
LABEL
ATC
DEFAULT
0
DESCRIPTION
Attenuator Control Mode:
0 : Right channels use Right
attenuation
1:
Right Channels use Left
Attenuation
Table 17 Attenuation Control Select
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be inverted.
REGISTER ADDRESS
0011
Interface Control
BIT
4
LABEL
REV
DEFAULT
0
DESCRIPTION
Analogue Output Phase
0: Normal
1: Inverted
Table 18 Output Phase Control
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the
inverse of that shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11.
REGISTER ADDRESS
0011
Interface Control
BIT
5
LABEL
BCP
DEFAULT
0
DESCRIPTION
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
Table 19 BCKIN Polarity Control
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