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| 型號(hào)： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫參考平臺(tái)硬件設(shè)計(jì)手冊(cè) |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 17 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
4.0 Board Conguration
One design goal of the reference platform was the minimization of conguration jumpers.
Some are regrettably necessary due to the need to support a wide variety of processors.
The following sections describe all the jumpers in detail.
4.1 User-Settable Jumpers
Two or three pin “Berg” jumpers are used when user-changable options must be set.
4.1.1 System Frequency Selection
Jumpers J61, J34, and J32 ar e used to set the operating frequencies of the processor bus
and the PCI bus.
4.1.2 Processor Frequency Selection
Jumpers J35, J36, J38 and J40 are used to set the core, or internal, operating speed of the
processor. This is the speed at which the processor performs instructions, as opposed to
the speed at which it performs memory accesses. The core speed is always an integer or
half-integer multiple of the “Bus Clock” speed selected with the System Frequency jump-
ers.
Table 5: Clock Settings
J61
FS0
J34
FS1
J32
FS2
Bus
Clock
PCI
Clock
IN
50 MHz
25 MHz
IN
out
60 MHz
30 MHz
IN
out
IN
66 MHz
33 MHz
IN
out
75 MHz
37 MHz
out
IN
83 MHz
33 MHz
out
IN
out
90 MHz
30 MHz
out
IN
100 MHz
39 MHz
out
100 MHz
50 MHz
Table 6: Processor Clock Settings
J35
CP0
J36
CP1
J
38
CP2
J40
CP3
PLL
Bus
Clock
Core
Clock
IN
7X
IN
out
IN
out
IN
out
BYPASS
IN
out
IN
2X
60 ... 100
120 ... 200
IN
out
IN
out
6.5X
IN
out
IN
2.5X
50 ... 100
125 ... 250
IN
out
4.5X
50 ... 60
225 ... 300
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