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| 型號(hào)： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫參考平臺(tái)硬件設(shè)計(jì)手冊(cè) |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 10 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
Separate 31.3344 MHz and 50 MHz oscillators are provided for the Hydra device, which
is used exclusively MacOS related functions (Apple I/O, MESH SCSI controller, timers,
etc.).
All clocks have unoccupied pads for 0805-type devices which can be used to attenuate
clocks or adjust skew. These parts are not installed unless needed to meet radiated emis-
sions standards.
CHANGES: X4 extensively changes the clocking system to accomodate the faster bus
speeds, different PLL multipliers of the MPC106 (3:2 and 5:2 modes are added), and the
need for many more clock signals for SDRAM support. Additionally, to support board
testing below 50 MHz bus speeds, an external clock can be supplied to the MPC972,
which can generate the proper bus, SDRAM and PCI clocks. Note that the PAL control-
ling the MPC972 dividers may need to be re-programmed to maintain the proper relation-
ships between bus and PCI clocks that the MPC106 requires.
2.7 PCI-to-ISA Bridge
The PCI-to-ISA bridge provides a means of accessing ISA devices as well as integrating
several system using the W83C553 component from Winbond. Pullup resistors congure
this part to operate in “PowerPC Mode”, which congures the part to generate HRESET
and adds the additional REQ4#/GNT4# arbiter controls.
An external 74F138 is used to convert the encoded DMA acknowledge signals to individ-
ual strobes (this saves a few pins on the bridge devices). A Fast part was specied solely
due to its availability. Due to the relatively slow speed of the ISA bus, an LS138 or other
equivalent-speed technology would be acceptable.
A small transistor drives a connector that would be attached to an 8-ohm speaker, to create
the power-up “beep” or other low-quality sounds.
CHANGES: X4 removes the separate reset controller and uses the reset circuitry in the
Winbond part. The Winbond also controls the access to the boot EPROM, which is now
located on the ISA bus. The bridge chip responds to memory accesses immediately after
reset.
IN
out
30 MHz
60 MHz
30 MHz
IN
out
IN
33 MHz
66 MHz
33 MHz
IN
out
25 MHz
75 MHz
37 MHz
out
IN
33 MHz
83 MHz
33 MHz
out
IN
out
30 MHz
90 MHz
30 MHz
out
IN
33 MHz
100 MHz
39 MHz
out
25 MHz
100 MHz
50 MHz
Table 2: Clock Options
J61
FS0
J34
FS1
J32
FS2
CDC9843
MPC972
Base
Clock
Bus
Clock
SDRAM
Clock
PCI
Clock
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