參數(shù)資料
型號: YKNIFEX4HW
英文描述: IC APEX 20KE FPGA 100K
中文描述: 耶洛奈夫參考平臺硬件設(shè)計手冊
文件頁數(shù): 15/24頁
文件大小: 186K
代理商: YKNIFEX4HW
Yellowknife X4 Hardware Reference Manual
Page 21 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
5.0 Layout Issues
The guidelines detailed in the Yellowknife X2 hardware reference manual may be of help,
but the majority of the Yellowknife X4 layout is covered in great detail in the application
note AN17xx, “SDRAM System Design using the MPC106”. Here are some general
guidelines:
The VRM power supply module should be positioned close to the PGA socket,
such that the current ows through a heavy plane from the ATX power supply.
Insure placement of the VRM does not interfere with the HP analyzer header if
debugging is desired.
The VRM power supply capacitors should be positioned very near the CPU socket.
The following traces should be routed to carry additional current capacity:
5.1 Swappable Pins
The following groups may be pin-swapped (excluding the obvious swappable discrete
gates). Each line is considered a separate group.
MPC972
QA(0:3), QC(0:3)
QA/QC clock groups are swappable, as are
split-terminated outputs.
MPC972
QB(0:3)
QB clock groups are swappable, as are
split-terminated outputs.
IDT71216
A(12:0), TAG(11:1)
All except A13/TA13/TD13
MCM69P737
A(0:16)
Cache addresses swappable.
MCM69P737
DQ(0:63)
Cache data swappable (byte mode not used).
74ALVCH16601
A(1:18) :: B(1:18)
Input and output pairs swappable.
DIMM
D(0:7) :: DQMB0
Byte lanes and associated controls.
Table 13: Routing Power
Signal
Power
CORE_VDD
Sufcient for 7A.
TERMPWR
Sufcient for 1.5A.
J4
1A of +12V power (for fan).
J42-24
300mA
U11-28
100mA
VBAT
100mA
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