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| 型號(hào)： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫參考平臺(tái)硬件設(shè)計(jì)手冊(cè) |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 12 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
2.10 Interrupt Architecture
The following diagram shows the interrupt architecture for the Yellowknife. The use of
the MPIC allows the possibility of multi-processor interposers, though at this time none
are anticipated.
FIGURE 4. Interrupt Architecture
CHANGES: X4 adds a jumper to allow interrupts to from through the MPIC in Hydra
(for MacOS) or to bypass Hydra and connect the 8259 core in the Winbond bridge directly
to the processor. The latter is needed for embedded customers which will not need Hydra
and so do not wish to program for it.
2.11 Reset Architecture
The reset circuitry controls the global reset signals based upon the following sources:
x PWRGOOD
Low until the power supply has been stabilized; high there-
after.
x ADB_RESET#
Pulsed low by the ADB controller (due to a keyboard
sequence).
x RSTHDR#
Connected to ground by an external pushbutton switch (on
the chassis).
These reset sources are merged and connected to the South Bridge, which in turn resets the
rest of the system peripherals.
MPIC
Hydra
PCI
SLOTS
8259
PCI/ISA Bridge
ISA
SLOTS
15
Key
Super I/O
Mse
Par
Flop
IDE
PowerPC
MPC60X
JMPR
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