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參數(shù)資料
| 型號： | YSS943-VZ |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 封裝： | LEAD FREE, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 831K |
| 代理商： | YSS943-VZ |
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YSS944/943/940
17
Chip 2
Chip 3
nMICS
IOPORT3 to IOPORT0 = 2
IOPORT3 to IOPORT0 = 3
(b) Microprocessor interface connection example 2 (multiple LSIs)
When multiple LSIs are connected such as on
the left, or when the device has a similar
interface, access is performed using the register
byte ChipAdr (CAE, CA[3:0]).
Write ChipAdr
CAE = 1
CA[3:0] = 0011
Write ChipAdr
CAE = 1
CA[3:0] = 0010
Read ChipAdr
CAE = 1
CA[3:0] = 0011
On-chip memory access
nMICS
MI SI
0
1
0
CAE
(Chip 2, 3)
Internal signal
nMICS (Chip 2)
Internal signal
nMICS (Chip 3)
<1>
<2>
<3>
<4>
<5>
<1> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is
valid to for all LSIs (chips 2 and 3 in this example) that share the nMICS pin. In this case, CAE = 1
and CA[3:0] = 3, so only the access only for chip 3 is valid.
<2> A write operation to ChipAdr not immediately after the falling edge of nMICS is also invalid for chip
3.
(Chip 2 is not affected by the register access itself.)
<3> The ChipAdr register can be read at any time. In this case, the write results from <1> are read from
chip 3.
(Chip 2 is not affected by the register access itself.)
<4> During on-chip memory access, register access for chip 3 is invalid.
(Chip 2 is not affected by on-chip memory access.)
<5> CAE of all LSIs becomes zero at the rising edge of nMICS.
[Note]
The timing by which the chip selection is confirmed in <1> is determined by the value of IOPORT3 to
IOPORT0 either at:
the register access immediately after falling edge of nMICS, or
a write operation to ChipAdr.
Once the chip selection is confirmed, the current value is retained until the next rising edge of nMICS.
Accordingly, even if the selected chip’s own IOPORT3 to IOPORT0 values change, the chip does not
become deselected immediately.
When nMICS is shared by multiple chips:
CAE = 0 at the register access immediately after the falling edge of nMICS or CAE = 1 is not written.
CAE = 1 at the register access immediately after the falling edge of nMICS, but the values of IOPORT3
to IOPORT0 are the same for multiple LSIs.
In the above cases, the multiple LSIs that share nMICS become the selected devices. In such cases,
multiple LSIs can be written to at once, but note with caution that a conflict can occur with the MISO output
when they are read.
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