參數(shù)資料
型號: Z86C46
廠商: ZiLOG, Inc.
英文描述: CMOS Z8 MCU(CMOS Z8系列微控制器)
中文描述: 單片機的CMOS Z8的CMOS(Z8系列微控制器)
文件頁數(shù): 24/70頁
文件大小: 1192K
代理商: Z86C46
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
24
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS
(Continued)
Port 1 (P17–P10).
Port 1 is an 8-bit, bidirectional, CMOS-
compatible port (Figure 13), with multiplexed Address
(
A7–A0
) and Data (
D7–D0
) ports. For the ROM device,
these eight I/O lines are programmed as inputs or outputs,
or can be configured under software control as an Ad-
dress/Data port for interfacing external memory. The input
buffers are Schmitt-triggered and byte-programmed as out-
puts and can be globally programmed as either push-pull
or open-drain. Low-EMI output buffers can be globally pro-
grammed by the software.
Note:
Port 1 is not available on the devices in the 28-pin pack-
age, and
P01M
Register must set Bit
D4,D3
as
00
. Low-
EMI mode is not supported on the emulator for Port1.
PCON
register
D4
must be
1
.
Port 1 may be placed under handshake control. In this con-
figuration, Port 3, lines
P33
and
P34
are used as the hand-
shake controls
RDY1
and
DAV1
(Ready and Data Avail-
able). Memory locations greater than the internal ROM
address are referenced through Port 1, except for Z86C46.
To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional
lines.
Port 1 can be placed in the high-impedance state along with
Port 0,
AS
,
DS
, and
R/W
, allowing the Z8 to share common
resources in multiprocessor and DMA applications.
Figure 13. Port 1 Configuration
Open Drain
OE
Out
In
1.5 2.3 Hysteresis @ V
CC
= 5.0V
PAD
Auto Latch
(mask option)
R
500 K
Port 1
(I/O or AD7–AD0)
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Z8
8
Pull-Up
Transistor Enable
(Mask Option)
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