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參數(shù)資料
| 型號： | Z86C46 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 MCU(CMOS Z8系列微控制器) |
| 中文描述： | 單片機的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 48/70頁 |
| 文件大小： | 1192K |
| 代理商： | Z86C46 |
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
48
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI TRANSMIT DATA REGISTER (TDR)
(%(A)01H: READ/WRITE)
Data written to the ASCI Transmit Data Register (
transferred to the Transmit Shift Register (
the
TSR
is empty. The
TSR
The ASCI transmitter is double-buffered so data can be
TDR
0
) is
TSR
) as soon as
is not not software-accessible.
written to the
byte. Data can be written into and read out of the
the
TDR
is read, the data transmit operation is not affected.
TDR
while the
TSR
is shifting out the previous
TDR
. When
ASCI RECEIVE DATA REGISTER (RDR)
(%(A)02H: READ/WRITE)
When a complete incoming data byte is assembled in the
Receive Shift Register (
RSR
), it is automatically transferred
to the highest available location in the Receive Data FIFO.
The Receive Data Register (
RDR
the Receive Data FIFO. The
RDRF
bit in the
STAT
register
) is the highest location in
is set when one or more bytes is available from the FIFO.
The FIFO status for the character in the
RDR
is available
in the
STAT
register via bits
6
,
5
and
4
.
STAT
should be
read before reading the
RDR
. The data in both FIFO loca-
tions is
popped
when the character is read from the
RDR
.
ASCI CONTROL REGISTER A (CNTLA)
(%(A)03H: READ/WRITE)
Table 17. TDR Register Bit Functions
Bit
7
6
5
4
3
2
1
R
Transmit Data
W
Reset
U
U
U
U
U
U
U
U
Table 18. RDR Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Receive Data
W
Reset
U
U
U
U
U
U
U
U
Table 19. CNTLA Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Multiprocessor
Enable
(MPE)
Receiver
Enable
(RE)
Transmitter
Enable
(TE)
Reserved
Multiprocessor
Bit Received
(MPBR)
MOD2 MOD1 MOD0
W
Error Flag
Receive
(EFR)
Mode Select
Reset
0
0
0
1
0
0
0
0
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