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參數(shù)資料
| 型號： | Z86C83 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 Microcontroller(CMOS Z8系列微控制器) |
| 中文描述： | 微控制器的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 338K |
| 代理商： | Z86C83 |
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Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-32
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION
(Continued)
Interrupts.
The Z8 has six different interrupts from six dif-
ferent sources. These interrupts are maskable, prioritized
(Figure 20) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33-P30, and two in
counter/timers (Table 11). The Interrupt Mask Register
globally or individually enables or disables the six interrupt
requests.
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. An interrupt ma-
chine cycle is activated when an interrupt request is
granted. This action disables all subsequent interrupts,
saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved
for that interrupt.
Figure 20. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Name
IRQ0
IRQ1,
IRQ2
IRQ3
IRQ4
IRQ5
Source
/DAV0, IRQ0
IRQ1
/DAV2, IRQ2, T
IN
IRQ3
T0
T1
Vector Location
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
Comments
External (P32), Rise Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Rise Fall Edge Triggered
By User Software
Internal
Internal
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ1, 3, 4, 5
IRQ
IMR
IPR
PRIORITY
LOGIC
6
Global
Interrupt
Enable
Vector Select
Interrupt
Request
IRQ0 IRQ2
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