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參數(shù)資料
| 型號： | Z86C83 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 Microcontroller(CMOS Z8系列微控制器) |
| 中文描述： | 微控制器的CMOS Z8的CMOS（Z8系列微控制器） |
| 文件頁數(shù)： | 33/52頁 |
| 文件大小： | 338K |
| 代理商： | Z86C83 |
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Z86C83/C84/E83
CMOS Z8
MCU
Zilog
DS97DZ80700
P R E L I M I N A R Y
8-33
1
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge trig-
gered, and are programmable by the user. The software
may poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select is located
in the IRQ Register (R250), bits D7 and D6. The configu-
ration is shown in Table 12.
Clock.
The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, LC, ceramic
resonator, or any suitable external clock source (XTAL1 =
Input, XTAL2 = Output). The crystal should be AT cut, 16
MHz max., with a series resistance (RS) of less than or
equal to 100 Ohms when clocking from 1 MHz to 16 MHz.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor's recommended capacitor values
from each pin directly to the device Ground pin to reduce
Ground noise injection into the oscillator (Figure 21).
Note:
For better noise immunity, the capacitors should be
tied directly to the device Ground pin (V
SS
).
Table 12. IRQ Register
IRQ
Interrupt Edge
P31
F
F
R
R/F
D7
0
0
1
1
D6
0
1
0
1
P32
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Figure 21. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator or
Crystal
C1, C2 = 22 pF TYP *
f = 8 MHz
LC
External Clock
L
* Preliminary value including pin parasitics
* * Device ground pin
VSS* *
VSS* *
VSS* *
VSS* *
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