參數(shù)資料
型號： Z8S18006FEC
廠商： ZiLOG, Inc.
元件分類： 微處理器
英文描述： CAP 1UF 50V 10% X7R AXIAL TR-14
中文描述： 強(qiáng)化Z180微處理器
文件頁數(shù)： 1/70頁
文件大?。?/td> 387K
代理商： Z8S18006FEC
DS971800401
P R E L I M I N A R Y
1-1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z80180/Z8S180/
Z8L180 SL1919
E
NHANCED
Z180 M
1
ICROPROCESSOR
FEATURES
I
Code Compatible with Zilog Z80
CPU
I
Extended Instructions
I
Two Chain-Linked DMA Channels
I
Low Power-Down Modes
I
On-Chip Interrupt Controllers
I
Three On-Chip Wait-State Generators
I
On-Chip Oscillator/Generator
I
Expanded MMU Addressing (up to 1 MB)
I
Clocked Serial I/O Port
I
Two 16-Bit Counter/Timers
I
Two Enhanced UARTs (up to 512 Kbps)
I
Clock Speeds: 6, 8, 10, 20, 33 MHz
I
Operating Range: 5V (3.3V@ 20 MHz)
I
Operating Temperature Range: 0
°
C to +70
°
C
I
-40
°
C to +85
°
C Extended Temperature Range
I
Three Packaging Styles
–
68-Pin PLCC
–
64-Pin DIP
–
80-Pin QFP
GENERAL DESCRIPTION
The enhanced Z80180/Z8S180/Z8L180
proves on the previous Z80180 models while still providing
full backward compatibility with existing Zilog Z80 devices.
The Z80180/Z8S180/Z8L180 now offers faster execution
speeds, power saving modes, and EMI noise reduction.
significantly im-
This enhanced Z180 design also incorporates additional
feature enhancements to the ASCIs, DMAs, and I
STANDBY Mode power consumption. With the addition of
“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs
now have the flexibility and capability to transfer data asyn-
chronously at rates of up to 512 Kbps. In addition, the ASCI
receiver has added a 4-byte First In First Out (FIFO) which
can be used to buffer incoming data to reduce the inci-
dence of overrun errors. The DMAs have been modified to
allow for a “chain-linking” of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for non-stop DMA operation be-
tween the two DMA channels, reducing the amount of CPU
intervention (Figure 1).
cc
Not only does the Z80180/Z8S180/Z8L180 consume less
power during normal operations than the previous model,
it has also been designed with three modes intended to fur-
ther reduce the power consumption. Zilog reduced I
er consumption during STANDBY Mode to a minimum of
10
μ
A by stopping the external oscillators and internal
clock. The SLEEP mode reduces power by placing the
CPU into a “stopped” state, thereby consuming less cur-
rent while the on-chip I/O device is still operating. The
SYSTEM STOP mode places both the CPU and the on-
chip peripherals into a “stopped” mode, thereby reducing
power consumption even further.
cc
pow-
A new clock doubler feature has been implemented in the
Z80180/Z8S180/Z8L180 device that allows the program-
mer to double the internal clock from that of the external
clock. This provides a systems cost savings by allowing
the use of lower cost, lower frequency crystals instead of
the higher cost, and higher speed oscillators.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin
PLCC, and 64-pin DIP packages.
相關(guān)PDF資料
PDF描述
Z8S18006FSC CAP 0.47UF 50V 10% X7R AXIAL TR-14
Z8S18006PEC CAP 0.1UF 50V 2% NP0(C0G) AXIAL TR-14
Z8S18006PSC CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
Z90102 CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
Z90103 CAP 680PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Z8S18006FSC 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR
Z8S18006PEC 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR
Z8S18006PSC 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR
Z8S18006VEC 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR
Z8S18006VSC 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*