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參數資料
| 型號： | Z8S18006FEC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 1UF 50V 10% X7R AXIAL TR-14 |
| 中文描述： | 強化Z180微處理器 |
| 文件頁數： | 44/70頁 |
| 文件大小： | 387K |
| 代理商： | Z8S18006FEC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-44
P R E L I M I N A R Y
DS971800401
Transmit Enable (bit 4).
A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears TE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. TE and RE
are never both set to 1 at the same time. TE is cleared to
0 during RESET and IOSTOP mode.
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0).
SS2, SS1 and
SS0 select the CSI/O transmit/receive clock source and
speed. SS2, SS1 and SS0 are all set to 1 during RESET.
Table 10 shows CSI/O Baud Rate Selection.
After RESET, the CKS pin is configured as an external
clock input (SS2, SS1, SS0 = 1). Changing these values
causes CKS to become an output pin and the selected
clock is output when transmit or receive operations are en-
abled.
CSI/O Transmit/Receive Data Register
(TRDR: I/O Address = 0BH).
Timer Data Register Channel 0L
TMDR0L
0CH
Timer Data Register Channel 0H
TMDR0H
0D H
Table 7. CSI/O Baud Rate Selection
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Divide Ratio
÷
20
÷
40
÷
80
÷
160
÷
320
÷
640
÷
1280
External Clock Input
(less than
÷
20.)
Figure 41. CSI/O Transmit/Receive Data Register 1R
CSI/O T/R Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 42. Timer Register Channel OL
Figure 43. Timer Data Register Channel OH
ASCI Receive Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Timer Data
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
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相關代理商/技術參數 |
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| Z8S18006FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
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