參數(shù)資料
型號(hào)： Z8S18033FEC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： ENHANCED Z180 MICROPROCESSOR
中文描述： 8-BIT, MICROPROCESSOR, PQFP80
封裝： QFP-80
文件頁數(shù)： 64/70頁
文件大小： 387K
代理商： Z8S18033FEC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-64
P R E L I M I N A R Y
DS971800401
OPERATION MODE CONTROL REGISTER
Mnemonic OMCR
Address 3E
The Z80180/Z8S180/Z8L180 is descended from two dif-
ferent “ancestor” processors, Zilog's original Z80 and the
Hitachi 64180. The Operating Mode Control Register (OM-
CR) can be programmed to select between certain differ-
ences between the Z80 and the 64180.
M1E (M1 Enable).
This bit controls the M1 output and is
set to a 1 during reset.
When M1E=1, the M1 output is asserted Low during the
opcode fetch cycle, the INT0 acknowledge cycle, and the
first machine cycle of the NMI acknowledge.
On the Z80180/Z8S180/Z8L180, this choice makes the
processor fetch an RETI instruction once, and when fetch-
ing an RETI from zero-wait-state memory will use three
clock machine cycles which are not fully Z80-timing com-
patible but are compatible with the on-chip CTCs.
When MIE=0, the processor does not drive M1 Low during
instruction fetch cycles, and after fetching an RETI instruc-
tion once with normal timing, it goes back and re-fetches
the instruction using fully Z80-compatible cycles that in-
clude driving M1 Low. This may be needed by some exter-
nal Z80 peripherals to properly decode the RETI instruc-
tion.I/O Control Register (ICR).
ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode (Figure 84).
Figure 82. Operating Control Register
(OMCR: I/O Address = 3EH)
D7
Reserved
D6 D5 --
IOC (R/W)
M1TE (W)
M1E (R/W)
--
--
--
--
Figure 83. RETI Instruction Sequence with MIE=0
Figure 84. I/O Control Register (ICR: I/O Address = 3FH)
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
T
I
T
1
T
2
T
3
T
1
T
2
T
3
T
I
T
I
A
0
-A
18
(A
19
)
φ
D
0
-D
7
PC
PC+1
PC
PC+1
EDH
4DH
EDH
4DH
MREQ
M1
RD
ST
IOA7
IOA6
--
--
--
--
IOSTP
Bit
7
6
5
4
3
2
1
0
--
R/W
R/W
R/W
相關(guān)PDF資料
PDF描述
Z8S18033FSC CONN POWER HEADER 5ROW 10POS P-F
Z8S18033PEC ENHANCED Z180 MICROPROCESSOR
Z8S18033PSC ENHANCED Z180 MICROPROCESSOR
Z8S18033VEC CONN HDR INVERSE 30POS 5ROW R/A
Z8S18033VSC CONN HDR INVERSE 120POS 5ROW R/A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Z8S18033FEC00TR 功能描述:IC Z180 MPU 80QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
Z8S18033FEG 功能描述:微處理器 - MPU 33MHz STATIC Z180 XT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S18033FSC 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
Z8S18033FSC00TR 功能描述:IC Z180 MPU 80QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z180 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
Z8S18033FSG 功能描述:微處理器 - MPU 33MHz STATIC Z180 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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